openrisc / or1ksim

The OpenRISC 1000 architectural simulator
GNU General Public License v3.0
69 stars 43 forks source link

add support for atomic operation instructions #5

Closed skristiansson closed 10 years ago

skristiansson commented 10 years ago

This adds support for the atomic load-link/store-conditional instruction l.lwa and l.swa. In addition to that, tests that ensure their correct behaviour are also added.

2014-05-04 Stefan Kristiansson stefan.kristiansson@saunalahti.fi

* cpu/common/abstract.c:
(set_mem32) Clear atomic reserve on write to atomic address.
(set_mem16) Likewise.
(set_mem8) Likewise.
* cpu/common/execute.h <cpu_state>: Add loadlock_active and
loadlock_address members.
* cpu/or1k/except.c (except_handle): Clear atomic reserve on
exceptions.
* cpu/or32/insnset.c:
(l_swa): New function.
(l_lwa): Likewise.
* cpu/or32/or32.c <or1ksim_or32_opcodes>: Add l.lwa and l.swa
instructions.
* cpu/or32/simpl32-defs.h: Add l_swa and l_lwa declarations.
* cuc/load.c <conv>: Add l.lwa and l.swa instructions.

2014-05-04 Stefan Kristiansson stefan.kristiansson@saunalahti.fi

* or1ksim.tests/atomic.exp: New file. Test for atomic
(l.lwa/l.swa) instructions.

2014-05-04 Stefan Kristiansson stefan.kristiansson@saunalahti.fi

* atomic: New directory. Tests for l.lwa and l.swa atomic
        instructions.
* atomic/atomic.S: New file.
* atomic/Makefile.in: Likewise.
* atomic/Makefile.am: Likewise.
* Makefile.am: Add atomic test.
* configure.ac: Likewise.
* Makefile.in: Regenerated.
* configure: Likewise.
jeremybennett commented 10 years ago

Nice patch. Good to see you've added tests. I assume this needs no change to the documentation.

Please apply to master and or32 branches.