Error (10170): Verilog HDL syntax error at orpsoc_top.v(915) near text: ")"; mismatched closing parenthesis . Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Altera Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /fusesoc/build/sockit/src/sockit/rtl/verilog/orpsoc_top.v Line: 915
Error (10170): Verilog HDL syntax error at orpsoc_top.v(915) near text: ")"; expecting "(". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Altera Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /fusesoc/build/sockit/src/sockit/rtl/verilog/orpsoc_top.v Line: 915
It is a regression introduced by https://github.com/openrisc/orpsoc-cores/commit/d6d55297e78e09885f47b75f43d2c42bdf8329b7 . Just an orphaned bracket