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openrisc / orpsoc-cores

Core description files for FuseSoC
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atlys core fails to build with ise 14.7 #112

Open Fatsie opened 7 years ago

Fatsie commented 7 years ago

I can't build atlys core with ise 13.7. Output snippet I think is relevant:

WARNING:Route:436 - The router has detected an unroutable situation for one or more connections. The router will finish the rest of the
   design and leave them as unrouted. The cause of this behavior is either an issue with the placement or unroutable placement constraints.
   To allow you to use FPGA editor to isolate the problems, the following is a list of (up to 10) such unroutable connections:
     Unroutable      signal: dvi_clk     pin:  dvi_gen0/PCLK_GEN_INST/CLKIN
olofk commented 7 years ago

This is an old bug, and we haven't really figured out a consistent way to handle it. Problem is that it appears to appear at random. I ran into it the first time myself just some weeks ago, but it has been reported several times before https://github.com/openrisc/orpsoc-cores/issues/55 https://github.com/openrisc/orpsoc-cores/issues/77 https://github.com/openrisc/orpsoc-cores/issues/82 https://github.com/olofk/fusesoc/issues/45 I've been thinking about digging into this myself, but as I don't have the board anymore I wouldn't be able to verify the solution properly. The two known workarounds are to shuffle around the dvi_clk clock buffer or disable HDMI output completely

Fatsie commented 7 years ago

It's ISE 14.7, changed title. I only looked in open issues, not closed ones. I would like to keep HDMI output. I will look closer. Ideally DVI would be a fully open source generic core; current code is 'All Rights Reserved'