cores: adv_debug_sys: For X to zero during sim in crc module

openrisc / orpsoc-cores

Core description files for FuseSoC

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cores: adv_debug_sys: For X to zero during sim in crc module #12

Closed fjullien closed 11 years ago

fjullien commented 11 years ago

Signed-off-by: Franck Jullien franck.jullien@gmail.com

fjullien commented 11 years ago

This make OpenOCD happy. Do you think we could get rid of the ifdef ?

olofk commented 11 years ago

I haven't looked at the adv_dbg_if code enough to see if there is another way to do this, so I say that we go ahead and add this patch if it solves the problem for OpenOCD. If we want to push the patch upstream, we can take another look at it and see if anything needs to be changed.

I feel more comfortable with keeping the ifdef as I'm not familiar with the code, and having the ifdef reduces the chance that something goes wrong with the synthesis.