SoCkit openocd not working

celesbg2020 commented 3 years ago

Program FPGA

After building the sockit system with fusesoc I am able to program the .sof to the FPGA as shown below:

Info: Command: quartus_pgm --mode=jtag -o p;../../build/sockit_0/bld-quartus/sockit_0.sof@1 Info (213045): Using programming cable "CV SoCKit [1-2]" Info (213011): Using programming file ../../build/sockit_0/bld-quartus/sockit_0.sof with checksum 0x0483CB2B for device 5CSXFC6D6F31C8ES@1 Info (209060): Started Programmer operation at Fri Jul 31 09:31:32 2020 Info (209016): Configuring device index 1 Info (209017): Device 1 contains JTAG ID code 0x02D020DD Info (209007): Configuration succeeded -- 1 device(s) configured Info (209011): Successfully performed operation(s) Info (209061): Ended Programmer operation at Fri Jul 31 09:31:34 2020 Info: Quartus Prime Programmer was successful. 0 errors, 0 warnings Info: Peak virtual memory: 463 megabytes Info: Processing ended: Fri Jul 31 09:31:34 2020 Info: Elapsed time: 00:00:04 Info: Total CPU time (on all processors): 00:00:01

start openocd

However, I am having a problem while trying to run the openocd command from another terminal as shown below. Note: I build the openocd from this source (https://repo.or.cz/openocd.git) and build with the following features enabled. --enable-ftdi --enable-usb_blaster_libftdi --enable-maintainer-mode --

openocd -s /opt/toolchains/openocd/share/openocd/scripts/ -f interface/altera-usb-blaster2.cfg -f board/or1k_generic.cfg Open On-Chip Debugger 0.10.0-dev-00247-g73b676c (2016-03-20-13:27) Licensed under GNU GPL v2 For bug reports, read http://openocd.org/doc/doxygen/bugs.html Warn : Adapter driver 'usb_blaster' did not declare which transports it allows; assuming legacy JTAG-only Info : only one transport option; autoselect 'jtag' Info : vjtag tap selected Info : adv debug unit selected Info : Option 7 is passed to adv debug unit Info : set servers polling period to 1ms adapter speed: 3000 kHz Info : Altera USB-Blaster II found (Firm. rev. = 1.36) Info : This adapter doesn't support configurable speed Info : JTAG tap: or1200.cpu tap/device found: 0x02d020dd (mfg: 0x06e (Altera), part: 0x2d02, ver: 0x0) Info : adv debug unit is configured with option ADBG_USE_HISPEED Info : adv debug unit is configured with option ENABLE_JSP_MULTI Info : adv debug unit is configured with option ENABLE_JSP_SERVER Warn : Burst read timed out Warn : Burst read timed out Error: Burst read failed Error: Error while calling or1k_save_context Error: Error while calling or1k_debug_entry Polling target or1200.cpu failed, trying to reexamine Halting processor Info : Halt timed out, wake up GDB. Error: timed out while waiting for target halted

SoCkit development kit jumper settings

These are the settings to my SoCkit development kit:

1) JTAG chain switch -HSMC: Bypass -HPS : Bypass

2) FPGA Configuration Mode Switch

-AS(X4)

When I include the HPS in the jtag chain with the switch SW4 on the board , i get a different result from the Openocd as shown below:

openocd -s /opt/toolchains/openocd/share/openocd/scripts/ -f interface/altera-usb-blaster2.cfg -f board/or1k_generic.cfg Open On-Chip Debugger 0.10.0-dev-00247-g73b676c (2016-03-20-13:27) Licensed under GNU GPL v2 For bug reports, read http://openocd.org/doc/doxygen/bugs.html Warn : Adapter driver 'usb_blaster' did not declare which transports it allows; assuming legacy JTAG-only Info : only one transport option; autoselect 'jtag' Info : vjtag tap selected Info : adv debug unit selected Info : Option 7 is passed to adv debug unit Info : set servers polling period to 1ms adapter speed: 3000 kHz Info : Altera USB-Blaster II found (Firm. rev. = 1.36) Info : This adapter doesn't support configurable speed Info : JTAG tap: or1200.cpu tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd.), part: 0xba00, ver: 0x4) Warn : JTAG tap: or1200.cpu UNEXPECTED: 0x4ba00477 (mfg: 0x23b (ARM Ltd.), part: 0xba00, ver: 0x4) Error: JTAG tap: or1200.cpu expected 1 of 1: 0x02d020dd (mfg: 0x06e (Altera), part: 0x2d02, ver: 0x0) Info : JTAG tap: auto0.tap tap/device found: 0x02d020dd (mfg: 0x06e (Altera), part: 0x2d02, ver: 0x0) Error: Trying to use configured scan chain anyway... Warn : AUTO auto0.tap - use "jtag newtap auto0 tap -irlen 2 -expected-id 0x02d020dd" Error: IR capture error at bit 12, saw 0xFFFFFFFFFFFFFFD551 not 0x...3 Warn : Bypassing JTAG setup events due to errors Error: No VJTAG TAP instance found ! Error: TAP initialization failed Error: Couldn't read the CPU state Error: No VJTAG TAP instance found ! Error: TAP initialization failed Warn : Debug IF CPU control reg read failure. Warn : Resetting JTAG TAP state and reconnectiong to debug IF. Error: No VJTAG TAP instance found ! Error: TAP initialization failed Warn : ...attempt 1 of 5 Error: No VJTAG TAP instance found ! Error: TAP initialization failed Warn : Debug IF CPU control reg read failure. Warn : Resetting JTAG TAP state and reconnectiong to debug IF. Error: No VJTAG TAP instance found ! Error: TAP initialization failed Warn : ...attempt 2 of 5 Error: No VJTAG TAP instance found ! Error: TAP initialization failed Warn : Debug IF CPU control reg read failure. Warn : Resetting JTAG TAP state and reconnectiong to debug IF. Error: No VJTAG TAP instance found ! Error: TAP initialization failed Warn : ...attempt 3 of 5 Error: No VJTAG TAP instance found ! Error: TAP initialization failed Warn : Debug IF CPU control reg read failure. Warn : Resetting JTAG TAP state and reconnectiong to debug IF. Error: No VJTAG TAP instance found ! Error: TAP initialization failed Warn : ...attempt 4 of 5 Error: No VJTAG TAP instance found ! Error: TAP initialization failed Warn : Debug IF CPU control reg read failure. Warn : Resetting JTAG TAP state and reconnectiong to debug IF. Error: No VJTAG TAP instance found ! Error: TAP initialization failed Warn : ...attempt 5 of 5 Error: Could not re-establish communication with target Error: Error while calling or1k_is_cpu_running Polling target or1200.cpu failed, trying to reexamine Error: No VJTAG TAP instance found ! Error: TAP initialization failed Error: Couldn't read the CPU state Examination failed, GDB will be halted. Polling again in 100ms Error: No VJTAG TAP instance found ! Error: TAP initialization failed Warn : Debug IF CPU control reg read failure. Warn : Resetting JTAG TAP state and reconnectiong to debug IF. Error: No VJTAG TAP instance found ! Error: TAP initialization failed Warn : ...attempt 1 of 5 Error: No VJTAG TAP instance found ! Error: TAP initialization failed Warn : Debug IF CPU control reg read failure. Warn : Resetting JTAG TAP state and reconnectiong to debug IF. Error: No VJTAG TAP instance found ! Error: TAP initialization failed Warn : ...attempt 2 of 5 Error: No VJTAG TAP instance found ! Error: TAP initialization failed Warn : Debug IF CPU control reg read failure. Warn : Resetting JTAG TAP state and reconnectiong to debug IF. Error: No VJTAG TAP instance found ! Error: TAP initialization failed Warn : ...attempt 3 of 5 Error: No VJTAG TAP instance found ! Error: TAP initialization failed Warn : Debug IF CPU control reg read failure. Warn : Resetting JTAG TAP state and reconnectiong to debug IF. Error: No VJTAG TAP instance found ! Error: TAP initialization failed Warn : ...attempt 4 of 5 Error: No VJTAG TAP instance found ! Error: TAP initialization failed Warn : Debug IF CPU control reg read failure. Warn : Resetting JTAG TAP state and reconnectiong to debug IF. Error: No VJTAG TAP instance found ! Error: TAP initialization failed Warn : ...attempt 5 of 5 Error: Could not re-establish communication with target Error: Error while calling or1k_is_cpu_running Polling target or1200.cpu failed, trying to reexamine Error: No VJTAG TAP instance found ! Error: TAP initialization failed Error: Couldn't read the CPU state Examination failed, GDB will be halted. Polling again in 300ms Halting processor Warn : Target was in unknown state when halt was requested Error: No VJTAG TAP instance found ! Error: TAP initialization failed Error: Impossible to stall the CPU

I have already changed the FPGA jtag id in or1k_generic.cfg file using the info obtained with the jtagconfig command jtagconfig 1) CV SoCKit [1-2]
02D020DD 5CSEBA6(.|ES)/5CSEMA6/.. 4BA00477 SOCVHPS
In the altera_sockit.cfg file I found this comment openocd does not currently support the on-board USB Blaster II. Install the JTAG header and use a USB Blaster instead.

So shall I use an external USB-Blaster-II by mounting a jtag header on the board? Do I miss anything during those steps, or am I completely wrong? Thanks in advance.

fjullien commented 3 years ago

I think I remember the JTAG clock was way too fast (something about 25MHz, you should check if you can). I did this years ago, when I was working on it: https://github.com/fjullien/openOCD/commit/0c834568e020ed3b61a055086d9d142f03860e0f You should rebase this commit and give it a try.

celesbg2020 commented 3 years ago

Thank you !! changing the JTAG clock solves the problem. However, I used the jtagconfig command to change the JTAG clock. See details on page 15 of the following document. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-intel-fpga-download-cable-ii.pdf

I have another question. Now I am trying to run a simple helloworld on the mor1kx cpu. How can I be able to see the output on a UART console? Because connecting the USB-UART cable to the board I cant see anything on the UART terminal after loading the .elf. The baudrate is set for 115200.

target remote :50001 load set $npc=0x100 continue

Thank you in advance for your help.

fjullien commented 3 years ago

See details on page 15 of the following document.

Cool, we didn't have any documentation for USB-Blaster II when I wrote the OpenOCD code ! It would be great to know what commands jtagconfig sends to the USB-Blaster II and implement this in the OpenOCD driver.

About your problem, can you single step to see if at least something gets executed ?

fjullien commented 3 years ago

Can you try a led blinker first ?

celesbg2020 commented 3 years ago

gdb terminal:

Remote debugging using localhost:3333 0x00000700 in _or1k_reset () Loading section .vectors, size 0x2000 lma 0x0 Loading section .init, size 0x28 lma 0x2000 Loading section .text, size 0x4e00 lma 0x2028 Loading section .fini, size 0x1c lma 0x6e28 Loading section .rodata, size 0x1c lma 0x6e44 Loading section .eh_frame, size 0x4 lma 0x8e60 Loading section .ctors, size 0x8 lma 0x8e64 Loading section .dtors, size 0x8 lma 0x8e6c Loading section .jcr, size 0x4 lma 0x8e74 Loading section .data, size 0xc74 lma 0x8e78 Start address 0x100, load size 31468 Transfer rate: 238 KB/sec, 2097 bytes/write. npc (/32): 0x00000100 (gdb) list 1 #include 2
3 int main(int argc, char* argv[]) { 4 printf("Hello World!\n"); 5 return 0; 6 } 7
(gdb) break main Breakpoint 1 at 0x23b4: file ../../mor1kx-2SE/software/helloworld/helloworld.c, line 4. (gdb) next Single stepping until exit from function _or1k_reset, which has no line number information. 0x00002030 in _or1k_start () (gdb)

Openocd terminal:

openocd -s /opt/toolchains/openocd/share/openocd/scripts/ -f interface/altera-usb-blaster2.cfg -f board/or1k_generic.cfg Open On-Chip Debugger 0.10.0-dev-00247-g73b676c (2016-03-20-13:27) Licensed under GNU GPL v2 For bug reports, read http://openocd.org/doc/doxygen/bugs.html Warn : Adapter driver 'usb_blaster' did not declare which transports it allows; assuming legacy JTAG-only Info : only one transport option; autoselect 'jtag' Info : vjtag tap selected Info : adv debug unit selected Info : Option 7 is passed to adv debug unit Info : set servers polling period to 1ms Info : Altera USB-Blaster II found (Firm. rev. = 1.36) adapter speed: 3000 kHz Info : JTAG tap: hps.cpu tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd.), part: 0xba00, ver: 0x4) Info : JTAG tap: or1200.cpu tap/device found: 0x02d020dd (mfg: 0x06e (Altera), part: 0x2d02, ver: 0x0) Info : adv debug unit is configured with option ADBG_USE_HISPEED Info : adv debug unit is configured with option ENABLE_JSP_MULTI Info : adv debug unit is configured with option ENABLE_JSP_SERVER Halting processor or1200.cpu: target state: halted Chip is or1200.cpu, Endian: big, type: or1k Target ready... Info : accepting 'gdb' connection on tcp/3333 npc (/32): 0x00000100 Warn : Burst read timed out

What does it mean the 'Burst read timed out' warning message I get from the openocd terminal while trying to step through the code.
I have also tried the timer.c taken from the de0_nano tutorial (https://github.com/openrisc/tutorials) but I dont see any activity on the leds.

Thank you again for your help in advance!

celesbg2020 commented 3 years ago

I think I used the wrong command previously. Could you please take a look at the new gdb terminal results I obtained.

Reading symbols from ../../mor1kx-2SE/software/helloworld/helloworld.elf...done. Remote debugging using localhost:3333 0x00002038 in _or1k_start () Loading section .vectors, size 0x2000 lma 0x0 Loading section .init, size 0x28 lma 0x2000 Loading section .text, size 0x4dfc lma 0x2028 Loading section .fini, size 0x1c lma 0x6e24 Loading section .rodata, size 0x1c lma 0x6e40 Loading section .eh_frame, size 0x4 lma 0x8e5c Loading section .ctors, size 0x8 lma 0x8e60 Loading section .dtors, size 0x8 lma 0x8e68 Loading section .jcr, size 0x4 lma 0x8e70 Loading section .data, size 0xc74 lma 0x8e74 Start address 0x100, load size 31464 Transfer rate: 225 KB/sec, 2097 bytes/write. npc (/32): 0x00000100 (gdb) step Single stepping until exit from function _or1k_reset, which has no line number information. 0x00002030 in _or1k_start () (gdb) step Single stepping until exit from function _or1k_start, which has no line number information.

Program stopped. 0x00002038 in _or1k_start () (gdb) disas Dump of assembler code for function _or1k_start: 0x00002030 <+0>: l.jal 0x5ff4 <_or1k_cache_init> 0x00002034 <+4>: l.nop 0x0 => 0x00002038 <+8>: l.jal 0x6c24 <_or1k_board_init_early> 0x0000203c <+12>: l.nop 0x0 0x00002040 <+16>: l.movhi r3,0x0

It seem the program stops at this line ( 0x00002038 <+8>:l.jal 0x6c24 <_or1k_board_init_early>). I have realized that _or1k_board_init_early is used by a board definition file (de0_nano.S). So I recompiled my helloworld.c code with or1k-elf-gcc using -mboard=de0_nano flag. I use this cause while checking the de0_nano.S file most of the parameters used (uart base address, clock frequency ) defined are similar to the SoCkit design. So I thought I can use the de0_nano board definition for compiling the c code. But I obtained the same result as before. If I cant use de0_nano.S board definition, where can I get the board definition for the SoCkit board? I am struggling to make this work and I really appreciate your help!

fjullien commented 3 years ago

I'm afk for some days. My be @stffrdhrn can give you some tips. He's our or1k guru 😁

stffrdhrn commented 3 years ago

I would ask to check if the binary works on the or1ksim simulator first. I have not used openocd for a while now. I have been working on the software side too much recently.

celesbg2020 commented 3 years ago

Instead of using the prebuild or1k-elf baremetal tool chain from the de0_nano tutorial, I build the toolchain from the source by updating the board support package for the sockit board. One thing I have also noticed is that the hps has to be defined first in the JTAG chain in the or1k.cfg file. In my case I included the hps jtag line it the top of the or1k-dev.tcl file before source [find target/or1k.cfg] line.

jtag newtap hps cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id 0x4BA00477

For me that solves the issues I had. Also regarding to UART, first I have to boot Linux on the hps to access the UART on the hps side. Therefore, finally I am able to see the helloworld example printing on the console.

I really appreciate all the assistance from here so far !!

fjullien commented 3 years ago

I'm glad you solved it. I also have a SoCkit and this may be useful for me at some point.

openrisc / orpsoc-cores