Open lollisoft opened 10 years ago
Hi,
It would help to know a bit about your environment. Are you using FuseSoC, or are you using the Xilinx tools (ISE/Vivado) directly? If you are using the Xilinx tools, are you using the GUI, or working on the command line.
You should do a fresh checkout. The generic system was bitrotted but stayed in the tree long after it was unusable. Your best option now is to use the or1200-generic or mor1kx-generic systems as a starting point for getting to know the CPU and environment. Running some simulations and looking at the instruction traces and waveforms are often helpful.
I haven't heard of anyone working on the XuLA2 board, but people tend to just turn up with ready made ports sometimes, so I wouldn't completely rule out that someone is cooking up something :)
We have also recently added Xilinx ISE support to FuseSoC so there are ports for two Xilinx-equipped boards that should be pushed soon. Both are using Spartan6 devices, so that might help a little if you want to use it as a starting point.
Don't hesitate to ask for more guidance if you need, and if you want more direct interaction, feel free to drop in at #openrisc on irc.freenode.net as well
//Olof
Hi,
I try to start with Xilinx tools directly. I want to learn the design flow of it and then optionally use these tools indirectly later. Using ISE Web Pack, I try to get up a project that can be relocated on hard drive and then get it synthesized without errors (CVS / include path issues I had). After that I plan to get one pin from my board connected to enable the LED blinking sample as of below.
1.) For hands on tutorial, I think I start with the LED blinking sample from my board vendor (no CPU). He also has a free book describing the flow to get the LED blinking.
2.) I'll start over with the or1200-generic and try to bring it alive on the board and repeat the blinking sample with a CPU.
BTW. I have ordered some books about FPGA design to start reading to get knowledge about what I'll do :-)
Lothar
Am 07.04.2014 um 13:45 schrieb Olof Kindgren:
Hi,
It would help to know a bit about your environment. Are you using FuseSoC, or are you using the Xilinx tools (ISE/Vivado) directly? If you are using the Xilinx tools, are you using the GUI, or working on the command line.
You should do a fresh checkout. The generic system was bitrotted but stayed in the tree long after it was unusable. Your best option now is to use the or1200-generic or mor1kx-generic systems as a starting point for getting to know the CPU and environment. Running some simulations and looking at the instruction traces and waveforms are often helpful.
I haven't heard of anyone working on the XuLA2 board, but people tend to just turn up with ready made ports sometimes, so I wouldn't completely rule out that someone is cooking up something :)
We have also recently added Xilinx ISE support to FuseSoC so there are ports for two Xilinx-equipped boards that should be pushed soon. Both are using Spartan6 devices, so that might help a little if you want to use it as a starting point.
Don't hesitate to ask for more guidance if you need, and if you want more direct interaction, feel free to drop in at #openrisc on irc.freenode.net as well
//Olof
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Hi,
I am really new to the FPGA stuff and tried to setup a project using OR1200.
I like to start with my board from XESS: http://www.xess.com/shop/product/xula2-lx25/ https://github.com/xesscorp/XuLA2
To get rid of the crippled down soft cores from xilinx, I thought to try OR1200.
My goal is to get a minimal system syntesized and one pin wired to the outside to get a LED blinking using a C/C++ application. (Probably by integrating it into the boot loader signaling read operations)
I probably need to get started with a small LED blinker sample using some plain logic.
Using the download orpsoc-cores-master as of 27.10.2013, I get the following problems:
Struggling with the wb_uart16550_model file (include), I tried to change this include to an absolute path: `include "C:\OR1200\cores\wb_bfm\wb_bfm_params.v"
This solved the error, but I am not sure if that is the correct way. How to setup include paths?
Then I got the wollowing errors:
ERROR:HDLCompiler:267 - "C:\OR1200\systems\generic\rtl\verilog\orpsoc_top.v" Line 192: Cannot find port wb_clk on this module ERROR:HDLCompiler:267 - "C:\OR1200\systems\generic\rtl\verilog\orpsoc_top.v" Line 193: Cannot find port wb_rst on this module ERROR:HDLCompiler:267 - "C:\OR1200\systems\generic\rtl\verilog\orpsoc_top.v" Line 194: Cannot find port slave_sel_i on this module ERROR:HDLCompiler:267 - "C:\OR1200\systems\generic\rtl\verilog\orpsoc_top.v" Line 204: Cannot find port wbm_sdt_o on this module ERROR:HDLCompiler:267 - "C:\OR1200\systems\generic\rtl\verilog\orpsoc_top.v" Line 217: Cannot find port wbs_sdt_i on this module
Is it wise to get the last version of the files (I have seen the generic folder is gone)?
And my last question: Does anyone work on the board to become supported? It would probably be more easy :-)
Thanks, Lothar