systems: add atlys board port

openrisc / orpsoc-cores

Core description files for FuseSoC

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Closed skristiansson closed 10 years ago

skristiansson commented 10 years ago

OpenRISC system for Digilent Atlys development board. Basically lifted 'as is' from the orpsocv2 port at: git://git.openrisc.net/stefan/orpsoc

TODO:

Rewrite dvi_gen (currently a hacked up Xilinx whitepaper)
Clean up the Xilinx MIG memory controller wrapper (and possibly generate the MIG with coregen on fly)
General cleanup and de-orpsocv2-fication

olofk commented 10 years ago

Looks good to me. There is some potential for cleanup, but we can do that later. Feel free to apply