Added module name as argument to wb_intercon_gen

openrisc / orpsoc-cores

Core description files for FuseSoC

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Added module name as argument to wb_intercon_gen #72

Closed bluecmd closed 10 years ago

bluecmd commented 10 years ago

This change allows a user to specify the module name for a wishbone interconnect. This is useful when you want to have two or more busses in your design.

olofk commented 10 years ago

Excellent! It's been on my todo list for some time. Feel free to apply, or I'll do it when I get back from vacation.