Closed heshamelmatary closed 10 years ago
I committed this: https://github.com/openrisc/orpsoc-cores/commit/7b02a538765b0ddbcbbd759b33312f786b491f39 which reverts the commit that I believe introduced this error. Please test and report back if that fixes your issue.
I pulled the latest commit, but unfortunately the same problem still exists. This is another full log file: https://docs.google.com/document/d/1YYyuGHPMc807zyp-euVhsQ8zlKclvz0xVZise9A6hFU/edit
For anyone who may come across this issue (and uses ISE 14.6), I followed Stefan advice of commenting out HDMI stuff, and this worked for me!
Hi,
I was trying to build atlys system and I got some errors. My platform is fedora 20 and using Xilinx ISE 14.6. The following is a tail of the output error log:
3 constraints not met. INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
Generating Pad Report.
1 signals are not completely routed. See the orpsoc_top.unroutes file for a list of all unrouted signals.
WARNING:Par:100 - Design is not completely routed. There are 1 signals that are not completely routed in this design. See the "orpsoc_top.unroutes" file for a list of all unrouted signals. Check for other warnings in your PAR report that might indicate why these nets are unroutable. These nets can also be evaluated in FPGA Editor by selecting "Unrouted Nets" in the List Window.
WARNING:Par:283 - There are 29 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 3 mins 14 secs Total CPU time to PAR completion: 3 mins 16 secs
Peak Memory Usage: 995 MB
Placer: Placement generated during map. Routing: Completed - errors found. Timing: Completed - 236 errors found.
Number of error messages: 0 Number of warning messages: 38 Number of info messages: 1
Writing design to file orpsoc_top.ncd
PAR done!
Process "Place & Route" failed INFO:TclTasksC:1850 - process run : Generate Programming File is done.
Full log of "fusesoc build atlys" is at the following link:
https://docs.google.com/document/d/1XKbPo4vVf4xJpCQ_8cXemwDKrv0fC_7svZ8bVZwfhec/edit