Build for Atlys Board errors out at Process "Place & Route"

[jvm3487]

Hi,

I just started using fusesoc. I was trying to build a generic soc for the Atlys board using the command "fusesoc build atlys", and I am having an issue where the build errors out in the "Place & Route" phase with the inability to route the signal "dvi_clk" (this is the only signal that failed). I found this post (not mine) which looks to be the same problem with a copy of the output of the attempted Xilinx build: http://pastebin.com/BXJPN3tT

I am using version 14.7 of the Xilinx ISE design suite. It looks like the signal is used in orpsoc_top.v and is an output of the component defined by clkgen.v. I tried to adjust the clock signals without any luck. Any help in pointing me in the right direction would be much appreciated.

Thanks, John

[olofk]

Hi,

I just tried this with ISE 14.6, and @skristiansson tried this with ISE 14.7. None of us can reproduce the problem. The Xilinx tools are unfortunately very good at producing random errors, so it's a bit hard to say what the problem is. The only thing I could of think of is to try and remove the BUFG in dvi_gen, and enable the commented BUFG in clkgen instead. There's also some warning about "DFS_OSCILLATOR_MODE not set to PHASE_FREQ_LOCK" that could be worth pursuing.

Hope this helps

[jvm3487]

Hi Olof,

Thanks for responding so quickly and for you and @skristiansson looking into this. This is my first time using the Xilinx tools versus the Altera tools I've used in the past. I implemented your first suggestion, and I was able to generate the programming file. I'm not exactly clear as to why this solved the problem since it seemed to just move the signal from one spot to another in the design. Here are the changes I made:

In clkgen.v: Enabled the commented BUFG Modified the line "assign dvi_clk_o = ..." to "assign dvi_clk_o = dcm0_clkdv;"

In dvi_gen_top.v: Commented out the signal "clk50m" Commented out the BUFG clk50m_bufgbufg Modified the line "assign clk50m = ..." to "assign clk50m_bufg = dvi_clk_i;" I also made the following change which I don't think modifies the original concept, but I wasn't positive: Within the DCM_CLKGEN # component, changed the line .CLKIN(clk50m), to .CLKIN(clk50m_bufg),

In atlys.ucf: Modified the line "NET "dvi_gen0/clk50m_bufg" ..." to "NET "dvi_clk" TNM_NET = "TNM_CLK50M";

Thanks once again, John

[wallento]

It may be related to the buffer instantiation settings, this is especially annoying with inout buffers..

[olofk]

Hi John,

Great to hear it worked out. My experience with Xilinx tools is that you should keep your buffers as high up in the design hierarchy as you can, and kep the close to ths clock source (inputs or DCMs). It's not a bullet-proof solution, but helps in some cases.

I'm closing this issue, but I would like to wait with the pull request until it has been tested on a board