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openrisc / orpsoc-cores

Core description files for FuseSoC
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fusesoc simulation with atlys #88

Open sgiaconi opened 8 years ago

sgiaconi commented 8 years ago

I'm getting the following message:

////////////////////////////////////////////////// Compiling /home/xxxx/Downloads/Opencore/orpsoc-build/build/atlys/src/elf-loader/elf-loader.c... Compiling /home/xxxx/Downloads/Opencore/orpsoc-build/build/atlys/src/elf-loader/vpi_wrapper.c... Making elf-loader.vpi from elf-loader.o vpi_wrapper.o... ../src/atlys/rtl/verilog/xilinx_ddr2/mcb_soft_calibration_top.v:81: warning: Numeric constant truncated to 10 bits. ../src/mor1kx/bench/verilog/mor1kx_monitor.v:42: Include file test-defines.v not found error: Unable to find the root module "orpsoc_tb" in the Verilog source. : Perhaps ``-s orpsoc_tb'' is incorrect? 1 error(s) during elaboration. ERROR: Failed to build simulation model ERROR: Failed to compile Icarus Simulation model /////////////////////////////

It seems like fusesoc does not provide the orpsoc_tb.v file.

What should I do?

Thanks, Stefano

olofk commented 8 years ago

Unfortunately there is no testbench at all available for the Atlys system. I see that atlys.core claims to support simulations with Icarus Verilog, but that's not correct.