openvizsla ov_ftdi issues

openvizsla / ov_ftdi

FT2232H-based USB sniffer

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issues

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run python3 ./ovctl.py -p ov3.fwpkg eep-program 10000 give a error "Error releasing interface: No such device"

#58 imatespl opened 5 months ago
0
Openvizsla sniffing nothing (but transfer amount continues to go up)

#57 jaysonlarose opened 1 year ago
5
Set maximum captured packet size to 1027

#56 desowin opened 1 year ago
2
Timestamps are not accurate if bus is suspended and resumed during the capture

#55 desowin opened 1 year ago
0
Feature request: Full-Speed PRE handling

#54 desowin opened 1 year ago
0
LibOV.ProtocolError: Checksum for response incorrect

#53 defencore opened 2 years ago
1
Feature request: USB generator

#52 desowin opened 2 years ago
1
README: Mention Wireshark 3.5.0 packet reassembly

#51 desowin opened 3 years ago
0
remove hardware/ov_3.2_design.pdf

#50 laf0rge closed 3 years ago
0
Question about 3.3 changes

#49 pk-mdt closed 3 years ago
1
Osmocom requested changes, second batch

#48 cibomahto closed 3 years ago
4
Fix building host software on macOS 11

#47 twam closed 3 years ago
0
Osmocom updates for v3.3 production run

#46 cibomahto closed 3 years ago
5
Connect mounting holes to GND plane

#45 cibomahto closed 3 years ago
0
Better gerbers

#44 cibomahto closed 3 years ago
0
Remove sponsor logos from PCB

#43 cibomahto closed 3 years ago
7
Errata: bad silk screen on P4 for 1.2v and 5v

#42 lf- closed 3 years ago
2
"Sigrok integration"

#41 dogtopus closed 1 year ago
1
better self-explanatory --help output

#40 laf0rge closed 4 years ago
0
Remove obsolete wireshark dissector

#39 desowin closed 4 years ago
0
s/fwpack/fwpkg/g

#38 dogtopus closed 4 years ago
0
Dandify build.py

#37 dogtopus closed 4 years ago
0
FPGA Models: XC6SLX9-2TQG144C vs. XC6SLX9-3TQG144C (speed)

#36 rljacobson opened 4 years ago
2
Add intercative bom to aid assembly

#35 TomKeddie closed 4 years ago
2
Port openvizsla to artix 7

#34 TomKeddie opened 4 years ago
0
Update README.md

#33 Hoernchen closed 4 years ago
0
Err - bad PID of 0f

#32 attie closed 5 years ago
5
Feature request: Filter SOF and/or NAKed transactions

#31 desowin opened 5 years ago
18
Use LINKTYPE_USB_2_0 pcap format

#30 desowin closed 4 years ago
28
Why MAX_PACKET_SIZE is set to 800?

#29 desowin opened 5 years ago
1
README: add a Getting Started section

#28 whitequark closed 5 years ago
0
README.md: add alternative shop

#27 artur-rs closed 5 years ago
0
ovctl: Add support for the ITI1480A session format

#26 smunaut closed 5 years ago
1
Error when building software for FPGA

#25 ar0mat opened 5 years ago
2
software/host: Fix "make clean"

#24 laf0rge closed 5 years ago
0
OV output problem

#23 wxh0000mm closed 5 years ago
0
Burn the firmware step file

#22 wxh0000mm closed 5 years ago
2
How do I see the analyzed USB datani

#21 wxh0000mm closed 5 years ago
3
OSError: no version directory for Xilinx tools found in /opt/Xilinx

#20 wxh0000mm closed 5 years ago
2
EEPROM programming issue

#19 ar0mat closed 5 years ago
5
Avoid conflict with async keyword in Python versions >= 3.5.

#18 thepsi closed 6 years ago
1
Output information from OV

#17 ar0mat closed 5 years ago
6
Libstdc++.so.6 error?

#16 marekm371 closed 6 years ago
13
Fix data trapping in SDRAM

#15 matwey opened 6 years ago
3
Fix build process & error propagation

#14 kopasiak closed 6 years ago
0
SDRAM data trapping

#13 matwey opened 6 years ago
6
Fix output build name

#12 matwey opened 6 years ago
2
Licensing and selling

#11 matwiszynmarek closed 6 years ago
1
Migrate FPGA firmware to the latest Migen

#10 matwey closed 6 years ago
9
Hardware for project

#9 tbutton closed 3 years ago
7