Open radwouters opened 1 month ago
See https://www.wch-ic.com/downloads/CH32V003RM_PDF.html and https://www.wch-ic.com/downloads/CH32V003RM_PDF.html
So, "sleep" mode in the RISC-V core is just entered with the wait for interrupt (WFI) or wait for event (WFE) instruction, these are already exposed via other file, e.g. core_riscv.h
,
// set PDDS = 0
PWR->CTLR &= ~(1u << 1u);
// set SLEEPDEEP=0 to not enter into standby mode, only sleep mode
PFIC->SCTLR &= ~(1u << 2u);
// goodnight
__WFI();
I think I understand what is happening here, but I am not sure how you got to it. Is there a place where I can see this translation from register to c code? For example how PWR->CTLR is PDDS?
It would also be possible to make a PR for this, right? So add a PWR_EnterSLEEPMode-method below here?
Please let me know if that would help the project :) Otherwise I'll just stay away from it!
In the datasheet of the CH32V003, section 2.3, it says that sleep is supported. When looking at ch32v00x_pwr.h, however, only the standby is implemented. Is there a reason for this? Would it be possible to use the same implementation as other chips and create a PR for this?
For my application, I would like to use sleep instead of standby, since I require a precise clock quickly after waking up. Also piggybacking a bit on #102