RTT implementation CH32V307

[sadkotheguest]

Hi! I'm trying to implement RTT (real-time-transfer) feature for debug and tracing of code with OpenOCD.

Wiki of Segger said that RTT background memory accesses are performed either via via RISC-V system bus access (SBA) or via AHB/AXI-AP. ( https://wiki.segger.com/RTT#RISC-V_specifics )

Could you tell - are SBA and/or AHB/AXI-AP access available in CH32V307 core? Have you tried to implement RTT or some similar soft for CH32V307?

[martinribelotta]

Some progress here? I'm working on it but need to enable/disable interrupt in nested way.

i found this in EVT/EXAM/SRC/Core/core_riscv.h:

__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __enable_irq()
{
  __asm volatile ("csrw 0x800, %0" : : "r" (0x6088) );
}

__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __disable_irq()
{
  __asm volatile ("csrw 0x800, %0" : : "r" (0x6000) );
}

But the documentation not said anything about CSR 0x800 (non standard extension)

I found this in the documentation (QingKeV4_Processor_Manual.PDF) but the excact data field is not mentioned:

If I read bits [15:0] of CSR 0x800 and restore it I can simulate multiple nested __disable_irq()/__enable_irq()? What others bitfield in CSR 0x800 is dangerous?

[martinribelotta]

Some updates:

• ginter is effectively 0x800
• Aparently, it is a shadow copy of mstatus in bits 3 and bit 7 (MPIE:7, MIE:3)
• This aparently disable/enable interrupts correct from user mode

The big problem now is enable RTT on openocd.

You can see the progress in my repository (add-rtt branch): https://github.com/martinribelotta/openwch-makefile/tree/add-rtt

[martinribelotta]

This is my probed code of disable_interrupt (and get state) and restore_interrupt for nested disable/enable interrupts:

static inline unsigned int disable_interrupt()
{
    unsigned int state;
    __asm__ volatile("csrr %0, 0x800\n\t"
                     "csrci 0x800, 8\n\t"
                     "andi %0, %0, 8\n\t"
                     : "=r"(state)
                     :
                     :);
    return state;
}

static inline void restore_interrupt(unsigned int state)
{
    __asm__ volatile("csrr a1, 0x800\n\t"
                     "or %0, %0, a1\n\t"
                     "csrs 0x800, %0\n\t"
                     :
                     : "r"(state)
                     : "a1");
}

[martinribelotta]

A patched wch openocd with rtt risc-v thread support can be found here: https://github.com/martinribelotta/openocd-wch/tree/rtt-riscv-wch-support

VSCode working with cortex-debug RTT support:

You can check the code in this repository: https://github.com/martinribelotta/openwch-makefile/tree/add-rtt