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optimsoc / optimsoc

OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
https://www.optimsoc.org
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Accomodating additional features: bootrom, cache #164

Open SRQ91 opened 5 years ago

SRQ91 commented 5 years ago

Currently in the OpTiMSoC source code, additional hardware such as bootrom, and data/inst. cache have been disabled. Is there any plan to include this functionality or would the design work with these activated?

Secondly, is there any documentation on how the default hardware flow of OpTiMSoC looks like for single/multicore versions? I mean this in terms of memory addressing etc.

imphil commented 5 years ago

Currently in the OpTiMSoC source code, additional hardware such as bootrom, and data/inst. cache have been disabled. Is there any plan to include this functionality or would the design work with these activated?

You can activate those features whenever you need them in your custom design. OpTiMSoC is meant to be a starting point for your own designs, giving you all necessary options to achieve that.

Secondly, is there any documentation on how the default hardware flow of OpTiMSoC looks like for single/multicore versions? I mean this in terms of memory addressing etc.

What do you mean by that? The hardware flow is always the same. The memory model is currently distributed between tiles, and and shared and coherent within a tile. In most example designs, all memory gets mapped to DRAM, e.g. in a four-tile system you end up with every tile having 1/4 of the DRAM, addressed from 0 to DRAMSIZE/4.