Native Image with SHA-IN on x86-64 platform

[Glavo]

Intel has provided Intel SHA extensions for accelerating SHA starting from Goldmont/IceLake. Unfortunately, native images do not seem to have a preset machine type (except for the native) that supports this extension:

On AMD64, the following machine types are available:

'compatibility'
  CPU features: all of 'x86-64'
'haswell'
  CPU features: all of 'x86-64' + SSE3 + SSSE3 + SSE4_1 + SSE4_2 + POPCNT + LZCNT + AVX + AVX2 + AES + CLMUL + BMI1 + BMI2 + FMA
'native'
  CPU features: CX8 + CMOV + FXSR + HT + MMX + AMD_3DNOW_PREFETCH + SSE + SSE2 + SSE3 + SSSE3 + SSE4_1 + SSE4_2 + POPCNT + LZCNT + TSC + TSCINV_BIT + AVX + AVX2 + AES + ERMS + CLMUL + BMI1 + BMI2 + ADX + SHA + FMA + VZEROUPPER + FLUSH + FLUSHOPT + CLWB + SERIALIZE + RDTSCP + RDPID + FSRM + F16C + PKU + CET_IBT + CET_SS
'skylake'
  CPU features: all of 'haswell' + AMD_3DNOW_PREFETCH + ADX + FLUSHOPT
'skylake-avx512'
  CPU features: all of 'skylake' + AVX512F + AVX512DQ + AVX512CD + AVX512BW + AVX512VL + CLWB
'x86-64'
  CPU features: CX8 + CMOV + FXSR + MMX + SSE + SSE2
'x86-64-v1'
  CPU features: all of 'x86-64'
'x86-64-v2'
  CPU features: all of 'x86-64-v1' + SSE3 + SSSE3 + SSE4_1 + SSE4_2 + POPCNT
'x86-64-v3'
  CPU features: all of 'x86-64-v2' + LZCNT + AVX + AVX2 + BMI1 + BMI2 + FMA
'x86-64-v4'
  CPU features: all of 'x86-64-v3' + AVX512F + AVX512DQ + AVX512CD + AVX512BW + AVX512VL

So,

• Can you provide some newer machine types (e.g. icelake)?
• Can you provide a more flexible way to enable these extended instructions? For example, is it possible to make native-image compatible with -XX:+UseSHA256Intrinsics, -XX:+UseAES, etc. options?

[mur47x111]

We are working on porting SHA stubs. Currently we don't support options such as -XX:+UseAES. You can disable individual intrinsics via -H:DisableIntrinsics, e.g., -H:DisableIntrinsics='AESCrypt.*'. See InvocationPlugins.java, MethodFilterHelp.txt

[fniephaus]

Can you provide some newer machine types (e.g. icelake)?

We currently only support machine types for which the Graal compiler can actually emit instructions. icelake, for example, adds new AVX-512 instruction subsets, which Graal does not use yet. In this case, it makes sense to pick the latest compatible machine type (e.g., skylake-avx512 if you want to use some AVX-512 instructions). We will add newer machine types when Graal can actually make use of their instructions.

[Glavo]

We currently only support machine types for which the Graal compiler can actually emit instructions. icelake, for example, adds new AVX-512 instruction subsets, which Graal does not use yet. In this case, it makes sense to pick the latest compatible machine type (e.g., skylake-avx512 if you want to use some AVX-512 instructions). We will add newer machine types when Graal can actually make use of their instructions.

Ok, I see.

We are working on porting SHA stubs. Currently we don't support options such as -XX:+UseAES. You can disable individual intrinsics via -H:DisableIntrinsics, e.g., -H:DisableIntrinsics='AESCrypt.*'. See InvocationPlugins.java, MethodFilterHelp.txt

OK. I'm looking forward to Graal's support for SHA-NI instructions, it can speed up some applications by several times.

[mur47x111]

We have ported all message digest stubs with 293cff16a2542f6ca1a09a52600dfffae7d27a3a and 5d60297d1de65ecfcd5bef087e8660282767cab6