Hi, is there any documentation or API reference guide for programming the OrangeCrab and targeting the RISC-V ISA? I noticed that in https://github.com/gregdavill/OrangeCrab-examples/blob/main/riscv/button/main.c there were calls to functions such as timer0_en_write() and rgb__r_write(), so is there any central doc that has peripheral documentation? Thanks.
When loading RISCV code directly as the examples illustrate, what is actually running this code is the SoC loaded into the FPGA by the bootloader. This processor is a bit limited, it currently only runs at 12MHz and does not contain a DDR3 memory controller.
This is the project for the bootloader: https://github.com/gregdavill/foboot/tree/OrangeCrab
Right now we don't have a referenced document about register maps for that SoC. We should set one up.
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When loading RISCV code directly as the examples illustrate, what is actually running this code is the SoC loaded into the FPGA by the bootloader. This processor is a bit limited, it currently only runs at 12MHz and does not contain a DDR3 memory controller. This is the project for the bootloader: https://github.com/gregdavill/foboot/tree/OrangeCrab
Right now we don't have a referenced document about register maps for that SoC. We should set one up.
LiteX has a mechanism to generate very nice HTML documentation for register maps, but we're currently not storing this anywhere. https://github.com/gregdavill/foboot/blob/OrangeCrab/hw/foboot-bitstream.py#L335