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oreboot / oreboot

oreboot is a fork of coreboot, with C removed, written in Rust.
GNU General Public License v2.0
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feature: visionfive2: use `jh71xx-hal` for peripheral access #715

Closed rmsyn closed 8 months ago

rmsyn commented 9 months ago

Uses the jh71xx-hal crate for peripheral access, mainly the UART0 peripheral.

The jh71xx-hal is currently a work-in-progress. Most notably, the interrupt code around PLIC configuration is apparently broken. The GPIO code also requires a big rewrite to match code from other embedded-hal implementations.

Depends on the changes in https://github.com/oreboot/oreboot/pull/713

codecov[bot] commented 9 months ago

Codecov Report

Attention: 6 lines in your changes are missing coverage. Please review.

Comparison is base (1d1f78b) 0.20% compared to head (d696156) 0.21%.

Files Patch % Lines
src/soc/src/sunxi/d1/gpio.rs 0.00% 4 Missing :warning:
src/mainboard/starfive/visionfive2/bt0/src/pac.rs 0.00% 2 Missing :warning:
Additional details and impacted files ```diff @@ Coverage Diff @@ ## main #715 +/- ## ===================================== Coverage 0.20% 0.21% ===================================== Files 23 22 -1 Lines 962 938 -24 ===================================== Hits 2 2 + Misses 960 936 -24 ```

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rmsyn commented 8 months ago

There are some formatting fixes, and a minor build fix needed. Other than that, ready to review.

rmsyn commented 8 months ago

Moving the Serial trait to the soc library will require a lot of rework.

Moving the trait causes cyclic dependencies, so it's going to take me more time to think about the required architecture changes.

orangecms commented 8 months ago

Awesome! 🥳 I'll try this out. looking good :)