Adding new benchmarks : ql_designs and IWLS2005

[thierryBesson]

We need to add these two set of benchmarks:

they are currently under "khyber" server under /tmp/TB_BENCHS

[thierryBesson]

Hi Awais and Aram,

I just set up some benchmarks of IWLS2005 set and from QuiclLogic suite and I would like to know if you can pick them up and install them in the appropriate places (Awais can you add them in the official CGA RTL benchmarks and Aram in your own internal suite of benchmarks as we discussed with Georgi to run QoR) ?

I put everything under "khyper" under /tmp/TB_BENCHS : 2 directories "IWLS2005" (12 designs) and "ql_designs" (98 designs). I will clean it after you have done the transfer.

BTW, I opened a github issue "Adding new benchmarks : ql_designs and IWLS2005" (see below) but I do not have the rights yet to assign assignees. I will put you as assignees as soon as I have the rights.

Note that in "ql_designs" we have some pretty big designs (for instance "sctag" is around 280K luts !).

We should start to have a reasonable suite of benchmarks after that.

[nadeemyaseen-rs]

@thierryBesson the /tmp location is not a good location to share data. On RS servers we have SHARE directory at /home/users/SHARE . It is recommended to use SHARE directory as /tmp is cleaned by OS regularly. Also @awaisabbas-rs Please move the data from /tmp/TB_BENCHS to SHARE directory at earliest.

[thierryBesson]

I moved it to SHARE. But we need to delete it after that.

[aram-rs]

Hi @thierryBesson,

Currently in yosys_verific_rs repository we have classified existing benchmarks according to the HDL language (vhdl, sv, mixed_language). Should we keep the same approach when adding these new benchmarks or we can group just by the suite name (IWLS2005 and ql_designs)?

Thanks, Aram

[thierryBesson]

Apparently "ql_designs" are all verilog so I would put this dir under verilog (so under "verilog" we have a subdir "ql-designs"). For IWLS I see most designs verilog but two with VHDL so I would create a subdir IWLS under "verilog" with the verilog designs and 1 IWLS under "vhdl" with the two Vhdl designs (eth and leon3mp). This way we can see first what is verilog and what is vhdl and under these 2 dirs from which suite the designs come from.

[aram-rs]

The benchmarks have been addd into yosys_verific_rs repository with the following PR.