Missing designs are added

[awaisabbas-rs]

Hi @aram-rs

I have added the 3 missing designs for Golden suite, Please review if the paths are correct or not.

[aram-rs]

@awaisabbas-rs our framework currently is able to extract source RTL files from one directory (so all HDL files of the benchmark should be in the same directory) and now I see multiple directories containing HDL files under Verilog/Cores/OpenCores_designs/Arithmetic_Core/double_fpu directory, could you please provide exact path to benchmark RTL folder and the top module name (is it the one which contains config.tcl file ?) ?

[awaisabbas-rs]

@aram-rs

The correct path for double_fpu design is RTL_Benchmark/Verilog/Cores/OpenCores_designs/Arithmetic_Core/double_fpu/rtl

Top Module Name: fpu

Top HDL File: RTL_Benchmark/Verilog/Cores/OpenCores_designs/Arithmetic_Core/double_fpu/rtl/fpu_double.v

[aram-rs]

@awaisabbas-rs thank you, could you please also provide the same information for the bch_configurable_bm and aes-128-pipelined_encryption benchmarks ?

[awaisabbas-rs]

Hi @aram-rs,

Please find the detail for remaining 2 designs below

bch_configurable_bm HDL PATH: RTL_Benchmark/Verilog/Cores/OpenCores_designs/ECC_Core/bch_configurable/trunk/src TOP: test_bch_bm TOP HDL FILE: RTL_Benchmark/Verilog/Cores/OpenCores_designs/ECC_Core/bch_configurable/trunk/src/test_bch_bm.v

aes-128-pipelined_encryption HDL PATH: RTL_Benchmark/Verilog/Cores/OpenCores_designs/crypto_core/aes-128_pipelined_encryption/rtl/ TOP: Top_PipelinedCipher TOP HDL FILE: RTL_Benchmark/Verilog/Cores/OpenCores_designs/crypto_core/aes-128_pipelined_encryption/rtl/Top_PipelinedCipher.v