Initial LiteX build backend available.

[enjoy-digital]

Hello,

just for info, the initial Raptor build backend for LiteX is available at https://github.com/enjoy-digital/litex/tree/master/litex/build/osfpga.

Two designs have been created:

• test_blinky.py: Simple led blinker design.
• test_soc.py: Simple SoC design(with CPU/ROM/RAM/UART/TIMER, etc...) with possibility to select the CPU and customize the parameters. --help can be used to see the available parameter.

test_soc.py can be useful to easily generate test designs for Raptor:

• test build with PICORV32 CPU: ./test_soc.py --cpu-type=picorv32 --toolchain=raptor --build
• test build with VexRiscv CPU: ./test_soc.py --cpu-type=vexriscv --toolchain=raptor --build
• test build with additional integrated RAM: ./test_soc.py --cpu-type=vexriscv --integrated-main-ram-size=0x10000 --toolchain=raptor --build
• etc...

[alain-rs]

@avinasht-rs FYI

[alain-rs]

@enjoy-digital , I think this is just a bad cut and paste from one of the examples, this macro setting is unnecessary: https://github.com/enjoy-digital/litex/blob/eeed11edea24a2b654042101de29e0fdf4f55f30/litex/build/osfpga/osfpga.py#L38

A better example is this one:

https://github.com/RapidSilicon/Raptor/blob/main/tests/Testcases/aes_decrypt_fpga/aes_decrypt.tcl The 2 target architectures supported by Raptor at this point are GEMINI and MPW1 The device size setting is to force OpenFPGA to use the fixed size layout (As opposed to the dynamic sized layout that VPR would use by default).

[enjoy-digital]

Thanks @alain-rs, this is updated with https://github.com/enjoy-digital/litex/commit/8ccfc96b1a11c02e512045336d87dfc9b02e762f.

@avinasht-rs: I did my test with: ./test_soc.py --toolchain=raptor --device=gemini --cpu-type=serv --build (haven't run the full build since it seems to be long, but it does not seems to be crashing).