Closed w0lek closed 1 week ago
The problem was found during the experimenting, if Pin Planner pick up newly added port from HDL.
Steps to reproduce:
input a_; inside the module and2
input a_;
was
module and2 ( input a, input b, input clk, input reset, output reg c = 1'b0 );
become
module and2 ( input a, input a_, input b, input clk, input reset, output reg c = 1'b0 );
@volodymyrkochyn FYI
I can reproduce this with just open and close Pin Planner steps
Fix here: https://github.com/os-fpga/FOEDAG/pull/1654
@w0lek This is done. Please verify the issue.
The problem was found during the experimenting, if Pin Planner pick up newly added port from HDL.
Steps to reproduce:
input a_;
inside the module and2was
become