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os-fpga / yosys_verific_rs

Yosys + (Optional) Verific Integration
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Support PLL VCO output #777

Closed chungshien-chai closed 2 months ago

chungshien-chai commented 2 months ago

  1. This is to support PLL VCO output which modeled as FAST_CLK port

  2. Accurately set set control pin mode (mode might be set wrong when the pin is used in bidirectional, but so far it seems not impact the bitstream negatively - still we should fix it).