search

os-fpga / yosys_verific_rs

Yosys + (Optional) Verific Integration
Other
5 stars 6 forks source link

Update design editor config.json flow after extra wires are removed #789

Closed chungshien-chai closed 1 month ago

chungshien-chai commented 1 month ago

With recent change in design editor that remove extra wires, which had broken existing IO_DDR in config.json.

This minor change is to keep up with that code and simplify the existing flow in handling config.json with design editor changes.

(p/s: keep original link_instance_recursively() function in this PR)

chungshien-chai commented 1 month ago

@alaindargelas please approve this when you have time.