Connection not instantiated

[lwrage]

In the following model instantiate ExtSystem.impl. There's no connection from dev_d to dev_a instantiated. The opposite direction is fine.

extinputs.aadl

package ExtInputs
public
with Parts, SystemLevel;    
    system ExtSystem

    end ExtSystem;

    system implementation ExtSystem.impl
        subcomponents
            dev_d: device Parts::d;
            complete_system: system SystemLevel::st_system.impl; 
        connections
            conn1: feature dev_d.ext_int -> complete_system.system_int;
            conn2: feature complete_system.system_int -> dev_d.ext_int;
        flows
            Flow_total: end to end flow dev_d.Flow_data_source -> conn1 -> complete_system.Flow_system -> conn2 -> dev_d.Flow_data_sink;
        modes
            none;
        properties
            none;
    end ExtSystem.impl;

end ExtInputs;

parts.aadl

package Parts
public

    device a
        features
            a_in: in event data port;
            a_out: out data port;
            a_return_in: in data port;
            a_return_out: out data port;
    end a;

    device b
        features
            b_in: in data port;
            b_out: out data port;
            b_return_in: in data port;
            b_return_out: out data port;
    end b;

    feature group subsystem_int_type
        features
            data_in: in event data port; 
            data_out: out data port;
    end subsystem_int_type;

    device c
        features
            c_in: in data port;
            c_out: out data port;
    end c;

    feature group ext_int_type
        features
            data_in: in data port;
            data_out: out event data port;
    end ext_int_type;

    device d
        features
            ext_int: feature group ext_int_type;
        flows
            Flow_data_source: flow source ext_int.data_out;
            Flow_data_sink: flow sink ext_int.data_in;
    end d;

end Parts;

subsystem.aadl

package SubSystem
public
with Parts; 

    system st_subsystem
        features
            subsystem_int: feature group Parts::subsystem_int_type;
            --subsystem_int_in: in event data port;
            subsystem_int_out: out data port; 
            data_out2: out data port;
            data_in2: in data port;
        flows
            Flow_subsys_data: flow path subsystem_int.data_in -> data_out2;
            --Flow_subsys_data: flow path subsystem_int -> data_out2;
            --Flow_subsys_data: flow path subsystem_int_in -> data_out2;

            Flow_subsys_data_return: flow path data_in2 -> subsystem_int.data_out;
            --Flow_subsys_data_return: flow path data_in2 -> subsystem_int;
            --Flow_subsys_data_return: flow path data_in2 -> subsystem_int_out;
    end st_subsystem;

    system implementation st_subsystem.impl
        subcomponents
            dev_a: device Parts::a;
            dev_b: device Parts::b;
        connections
            conn1: feature subsystem_int.data_in -> dev_a.a_in;
            --conn1: feature subsystem_int_in -> dev_a.a_in;
            conn2: feature dev_a.a_out -> dev_b.b_in;
            conn3: feature dev_b.b_out -> data_out2;
            conn4: feature data_in2 -> dev_b.b_return_in;
            conn5: feature dev_b.b_return_out -> dev_a.a_return_in;
            conn6: feature dev_a.a_return_out -> subsystem_int.data_out;
            --conn6: feature dev_a.a_return_out -> subsystem_int_out;
        flows
            Flow_subsys_data: flow path subsystem_int.data_in -> conn1 -> dev_a -> conn2 -> dev_b -> conn3 -> data_out2;
            --Flow_subsys_data: flow path subsystem_int -> conn1 -> dev_a -> conn2 -> dev_b -> conn3 -> data_out2;
            --Flow_subsys_data: flow path subsystem_int_in -> conn1 -> dev_a -> conn2 -> dev_b -> conn3 -> data_out2;

            Flow_subsys_data_return: flow path data_in2 -> conn4 -> dev_b -> conn5 -> dev_a -> conn6 -> subsystem_int.data_out;
            --Flow_subsys_data_return: flow path data_in2 -> conn4 -> dev_b -> conn5 -> dev_a -> conn6 -> subsystem_int;
            --Flow_subsys_data_return: flow path data_in2 -> conn4 -> dev_b -> conn5 -> dev_a -> conn6 -> subsystem_int_out;

end st_subsystem.impl;

end SubSystem;

systemlevel.aadl

package SystemLevel
public
with Parts, SubSystem;

    system st_system
        features
            system_int: feature group Parts::subsystem_int_type;
            --system_int_in: in event data port;
            --system_int_out: out data port; 
        flows
            --Flow_system: flow path system_int.data_in -> system_int.data_out;     
            Flow_system: flow path system_int -> system_int;
            --Flow_system: flow path system_int_in -> system_int_out;
    end st_system;

    system implementation st_system.impl
        subcomponents
            subsys: system SubSystem::st_subsystem.impl;
            dev_c: device Parts::c;
        connections
            conn1: feature system_int -> subsys.subsystem_int;
            --conn1: feature system_int_in -> subsys.subsystem_int_in;
            conn2: feature subsys.data_out2 -> dev_c.c_in;
            conn3: feature dev_c.c_out -> subsys.data_in2;
            conn4: feature subsys.subsystem_int -> system_int;
            --conn4: feature subsys.subsystem_int_out -> system_int_out;
        flows
            --Flow_system: flow path system_int.data_in -> conn1 -> subsys.Flow_subsys_data -> conn2 -> dev_c -> conn3 -> subsys.Flow_subsys_data_return -> conn4 -> system_int.data_out;
            Flow_system: flow path system_int -> conn1 -> subsys.Flow_subsys_data -> conn2 -> dev_c -> conn3 -> subsys.Flow_subsys_data_return -> conn4 -> system_int;
            --Flow_system: flow path system_int_in -> conn1 -> subsys.Flow_subsys_data -> conn2 -> dev_c -> conn3 -> subsys.Flow_subsys_data_return -> conn4 -> system_int_out;
        modes
            none;
        properties
            none;
    end st_system.impl;

end SystemLevel;

[lwrage]

Reduced size example: The issue is caused by feature group fgi having the same names as fg but in a different order.

package issue636
public
    feature group fg
        features
            di: in data port;
            do: out data port;
    end fg;

    feature group fgi -- if names are different everything works
        features
            do: out data port;
            di: in data port;
        inverse of fg
    end fgi;

    system left
        features
            fgi: feature group fgi;
    end left;

    system rss
        features
            si: in data port;
            so: out data port;
    end rss;

    system right
        features
            fg: feature group fg;
    end right;

    system implementation right.i
        subcomponents
            rss: system rss;
        connections
            c3: feature fg.di -> rss.si;
            c4: feature rss.so -> fg.do;
    end right.i;

    system top
    end top;

    system implementation top.i
        subcomponents
            left: system left;
            right: system right.i;
        connections
            c1: feature group left.fgi <-> right.fg;
    end top.i;

end issue636;