Closed philip-alldredge closed 8 years ago
In Oct/Nov 2011 we added the ability to associate ports with buses and memory. The rationale was that they can have modes and mode transitions are triggered by events. So if you wanted to model modal buses or memory you had no way of modeling that their modes are controlled externally. This was shortly before we approved AADL V2.1 and V2.1 does not contain this correction. For some reason I cannot find a record of this issue as an errata that was approved by the committee. I have noted the issue as an open errata for discussion at the next meeting.
Discussed and approved as errata at the Jan 2016 meeting.
An issue recently came up on the AADL modeling mailing list. OSATE allows ports to be created inside of Bus types. I don't recall any updates or errata on the subject so this appears to be an error.