Relax One_To_One bus access and binding of component arrays

[brlarson]

Currently, an "Array size mismatch" error is raised when trying to connect bus access from arrays of components to arrays of busses:

Array size mismatch (One_to_One) on connection a[1].to_bus -> b[1] in Example_replex_Instance: 1 at source and 4 at destination. Replex_Example_replex_Instance.aaxl2 /ReplicationExperiment/instances Unknown Instantiation Marker

Array size mismatch (One_to_One) on connection c[1].to_bus -> b[1] in Example_replex_Instance: 3 at source and 4 at destination. Replex_Example_replex_Instance.aaxl2 /ReplicationExperiment/instances Unknown Instantiation Marker

Array size mismatch (One_to_One) on connection m[1].to_bus -> b[1] in Example_replex_Instance: 3 at source and 4 at destination. Replex_Example_replex_Instance.aaxl2 /ReplicationExperiment/instances Unknown Instantiation Marker

When there are fewer components than buses, leave some buses unused. When there are more components than buses, wrap.

Do the same for Actual_XXXX_Binding too.

[lwrage]

Does the draft AADL 2.2 standard allow this?

[brlarson]

The standard doesn't say, but Peter is inclined to have a different enumeration literal for relaxed one-to-one. "Wrapped" would be my choice.

However, for bus access and bindings there's less of an issue. A checkbox for strict or permissive one-to-one on the OSATE preference pages would be fine.

On Jun 10, 2016, at 9:59 AM, Lutz Wrage notifications@github.com wrote:

Does the draft AADL 2.2 standard allow this?

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[lwrage]

This is a language issue and should be discussed on saeaadl/aadlv2.2 or saeaadl/aadlv3