X310 loopback frequency offset

[jmfriedt]

The X310 clocked by the reference 10 MHz exhibits a -4.5 Hz frequency offset despite the transmitted signal (GPIO output) to be exactly at 70 MHz (checked against reference source). The offset must be introduced on the receiver side.

Frequency offset of the receiving DDC? Might not be unrealistic with https://github.com/EttusResearch/fpga/blob/UHD-3.15.LTS/usrp3/lib/dsp/ddc_chain.v#L33 since log2(200e6/4.5)=25.405 so a resolution of +/-4.5 Hz on a 25-bit CORDIC?

[jmfriedt]

The X310 DDC has a finite frequency resolution that limits the accuracy as shown with

$ ./rx_samples_to_file --freq 70e6 --rate 5e6 --gain 20 --duration 10 usrp_samples.dat [...] Setting RX Freq: 70.000000000000 MHz... Setting RX LO Offset: 0.000000000000 MHz... Actual RX Freq: 70.000004768372 MHz...

The actual component source of the limitation remains to be identified, but at least the finite resolution is clearly documented by UHD.

[jmfriedt]

25 bit accumulator on a 200 MHz NCO or 24 bit accumulator on a 100 MHz NCO [1]: frequency tuning word is 70/200*2^25=11744051.2 rounding means the tuning word is either 11744051 or 11744052 (70-200*11744051/2^25)*1e6 = 1.19 Hz (70-200*11744052/2^25)*1e6 = -4.76837158 Hz is the correct answer so we understand the cause of the NCO error.

[1] https://github.com/EttusResearch/uhd/blob/master/fpga/usrp3/lib/ip/dds_sin_cos_lut_only/dds_sin_cos_lut_only.xci