The framebuffer is being written into dual port blockram so that it can be read-out in another clock domain, but this limits the size of the buffer. The ice40up5k has 1 Mib of single port ram, so it will need a fifo to copy the incoming scan line into the larger ram.
this will also be important if there is a riscv core doing any processing as part of #10
The framebuffer is being written into dual port blockram so that it can be read-out in another clock domain, but this limits the size of the buffer. The ice40up5k has 1 Mib of single port ram, so it will need a fifo to copy the incoming scan line into the larger ram.
this will also be important if there is a riscv core doing any processing as part of #10