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osresearch / pixel-wrangler

HDMI to whatever adapter
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TMDS D1 and D2 phases #23

Closed osresearch closed 1 year ago

osresearch commented 1 year ago

Are we getting 0-255 or 16-235?

osresearch commented 1 year ago

Blue gradient: image

Red gradient: image

Green gradient: image

It's not a full RGB issue, it appears to be a TMDS phase issue. The blue channel on D0 can synchronize on the vsync with all of its 01 transitions, but the D1 and D2 don't have that option. The 8b10b encoding for 0x00 and 0xFF have very few transitions, so out of phase means that the decoder mostly gets ok data for full on and full off. But if D1 and D2 are on different phases, they will have garbage.

osresearch commented 1 year ago

image

the control bits are the same on each channel:

image

and the patterns are image

osresearch commented 1 year ago

one idea is to dump the incoming bit stream from the d1 channel into DP block RAM and then have the uart dump it out.

this would require a serial port on the extra gpio pins.

osresearch commented 1 year ago

image

omg I think I see the problem. need to use DDR or non-DDR for all the tmds shift registers