Closed fcladera closed 3 years ago
I was able to synthesize this implementation, but I am still having some issues to generate the images using the old 2019.1 suite without Vitis. I think that creating this PR would be good to get some public feedback. Let's keep it as WIP until I am able to test it in hardware.
Thanks for the work! I never got around to updating the images for rev B, the fact that I didn't have any vectornav board didn't make it easy as well. For curiosity what issue are you having regenerating the images? Some sort of error at generation time or they get generated but don't boot?
Hi @luca-della-vedova! We got the external boards a couple of days ago, I'll follow up to ship you a couple without the VectorNav populated :)
I am struggling to build the different components required for the image. The boot.bif
file in the repo requires:
ovc/firmware/ovc3/test_board/vivado/test_board.sdk/fsbl/Debug/fsbl.elf
ovc3/test_board/vivado/test_board.sdk/pmufw/Debug/pmufw.elf
ovc3/test_board/vivado/test_board.runs/impl_1/zusys_wrapper.bit
ovc/firmware/ovc3/os/images/linux/bl31.elf
ovc/firmware/ovc3/os/images/linux/u-boot.elf
When trying to compile the TE0820 FSBL, it requires the file
BSP_DIR›:= ../misc/zynqmp_fsbl_bsp
which cannot be found on the files that TE provides.
I just observed that TE provides pre-built binaries for the fsbl and pmufw. Have you tried with these before?
Regarding the petalinux files, it also seems that you built them from scratch (os
folder). Would the pre-built ones work here?
Thanks!
When trying to compile the TE0820 FSBL, it requires the file
BSP_DIR›:= ../misc/zynqmp_fsbl_bsp
which cannot be found on the files that TE provides.
I'm not 100% sure what that file is. The workflow to build the FSBL was to start a new app project in XSDK for a Trenz modified FSBL, they provide a project template for a custom FSBL in their files (I found these instructions with a quick search). The BSP should be automatically generated when exporting the hardware from Vivado.
I just observed that TE provides pre-built binaries for the fsbl and pmufw. Have you tried with these before?
Sadly they won't work, pmufw / bl31 would probably be OK but you definitely need the FSBL to be custom. The FSBL is, among other things, in charge of doing all the register initialization to customize all the hardware peripherals (i.e. I2C, UART, USB, Ethernet), and it has to be built with the custom hardware. The images they provide only work for their carrier board.
Regarding the petalinux files, it also seems that you built them from scratch (
os
folder). Would the pre-built ones work here?
Same as above, you definitely need a custom built kernel image (image.ub) and FSBL (zynqmp_fsbl.elf), I'm not 100% sure of the others but they will be byproducts of the kernel image so might as well use the custom built ones.
Thanks for the feedback @luca-della-vedova. I was able to build both FSBL and PMUFW. I have also updated the instructions on the repo with a step-by-step guide. I am working on the kernel now.
Ok, just tested this with a VectorNav. I am receiving data on the ROS master from the VNAV.
I also updated the documentation with a mini-guide on how to generate the images.
I think it is good to go.
Hi everyone!
I started putting together the changes for the OVC 3B, to enable the VectorNav expansion board.
I was able to synthesize this implementation, but I am still having some issues to generate the images using the old 2019.1 suite without Vitis. I think that creating this PR would be good to get some public feedback. Let's keep it as WIP until I am able to test it in hardware.