After #160 is merged, we are missing the following.
Missing Instructions (0/14)
?
Inst
Ops
Enc
:white_large_square:
bvf
vfpu-branch
vfpu-branch
:white_large_square:
bvfl
vfpu-branch
vfpu-branch
:white_large_square:
bvt
vfpu-branch
vfpu-branch
:white_large_square:
bvtl
vfpu-branch
vfpu-branch
:white_large_square:
lvl.q
vfpu-load16
vfpu-memory-quad
:white_large_square:
lvr.q
vfpu-load16
vfpu-memory-quad
:white_large_square:
svl.q
vfpu-store16
vfpu-memory-quad
:white_large_square:
svr.q
vfpu-store16
vfpu-memory-quad
:white_large_square:
vcmovf
vfpu-condmove
vfpu-condmove
:white_large_square:
vcmovt
vfpu-condmove
vfpu-condmove
:white_large_square:
vcmp
vfpu-compare
vfpu-alu-compare
:white_large_square:
vmfvc
vfpu-control-read
vfpu-read-control
:white_large_square:
vmtvc
vfpu-control-write
vfpu-write-control
:white_large_square:
vwbn
vector-unary-mod
vector-imm8
Do note that lvl.q / lvr.q corrupt registers and when implemented, we should probably add a mitigation to save/restore the affected COP1 register. Shouldn't be too difficult to do with the existing macro magic.
After #160 is merged, we are missing the following.
Missing Instructions (0/14)
Do note that lvl.q / lvr.q corrupt registers and when implemented, we should probably add a mitigation to save/restore the affected COP1 register. Shouldn't be too difficult to do with the existing macro magic.