[ADC] Sampling time setting not available

[Ayoub-Farah]

To take longer time measurement, we could change ADC sampling time. However, it is currently not available in the ADC API.

[cfoucher-laas]

@Ayoub-Farah:

Sampling time can be configured in LL with the following values:

#define LL_ADC_SAMPLINGTIME_2CYCLES_5      (0x00000000UL)                                              /*!< Sampling time 2.5 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_6CYCLES_5      (                                        ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_12CYCLES_5     (                    ADC_SMPR2_SMP10_1                    ) /*!< Sampling time 12.5 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_24CYCLES_5     (                    ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 24.5 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_47CYCLES_5     (ADC_SMPR2_SMP10_2                                        ) /*!< Sampling time 47.5 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_92CYCLES_5     (ADC_SMPR2_SMP10_2                     | ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_247CYCLES_5    (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1                    ) /*!< Sampling time 247.5 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_640CYCLES_5    (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles */

The ADC driver we wrote hard-configures it to LL_ADC_SAMPLINGTIME_12CYCLES_5, with the following comment, dating from the legacy Riot driver:

    /* 000: 2.5 ADC clock cycles
     * 001: 6.5 ADC clock cycles
     * 010: 12.5 ADC clock cycles
     * 011: 24.5 ADC clock cycles
     * 100: 47.5 ADC clock cycles
     * 101: 92.5 ADC clock cycles
     * 110: 247.5 ADC clock cycles
     * 111: 640.5 ADC clock cycles
     */
    /* Vrefint minimum sampling time : 4us
     */
    /* Vts minimum sampling time : 5us
     */
    /* For 0b110:
     * Tadc_clk = 1 / 42.5 MHz = 23.5 ns
     * Tsar = 12.5 * Tadc_clk = 293.75 ns
     * Tsmpl = 247.5 * Tadc_clk = 5816.25 ns
     * Tconv = Tsmpl + Tsar = 6.11 us
     * -> Fconv up to 163.6 KSPS for 1 channel per ADC
     * Fconv up to 27.2 KSPS with the 6 channels actally
     * used on the ADC1
     *
     * For 0b001 (ok for voltage):
     * Tadc_clk = 1 / 42.5 MHz = 23.5 ns
     * Tsar = 12.5 * Tadc_clk = 293.75 ns
     * Tsmpl = 6.5 * Tadc_clk = 152.75 ns
     * Tconv = Tsmpl + Tsar = 446.4 ns
     * -> Fconv up to 2239 KSPS for 1 channel per ADC
     * Fconv up to 373 KSPS with the 6 channels actally
     * used on the ADC1
     *
     * For 0b101 (ok for current):
     * Tadc_clk = 1 / 42.5 MHz = 23.5 ns
     * Tsar = 12.5 * Tadc_clk = 293.75 ns
     * Tsmpl = 92.5 * Tadc_clk = 2173.75 ns
     * Tconv = Tsmpl + Tsar = 2.47 µs
     * -> Fconv up to 404 KSPS for 1 channel per ADC
     * Fconv up to 134 KSPS for 3 channels actally
     * used on each ADC
     */

Given we can't expose these complicated LL defines to the user, one option could be to add an enum with the available timings, as indicated in the above comment.

Plus, sampling time can be configured independently for each ADC channel if we want to. Do you think this would be relevant for our use cases, or one timing per ADC could be enough?

Any thoughts about these?

[jalinei]

Your proposal works for me @cfoucher-laas, an enum with the acquisition time seems good enough

[jalinei]

One per ADC is also good enough