Impacts the Front IO FPGAs which have I2C interfaces to transceiver modules, some of which may clock stretch. Also impacts the Mainboard FPGA as it has an I2C interface to the Tofino 2. In addition to clock stretching, the core will now also perform acknowledge-polling after all writes.
@mkeeter throwing you on here as I'm touching the transceiver thermal loop's port-disabling mechanism to add in another potential failure. The vast majority of the diff is general FPGA update noise.
Impacts the Front IO FPGAs which have I2C interfaces to transceiver modules, some of which may clock stretch. Also impacts the Mainboard FPGA as it has an I2C interface to the Tofino 2. In addition to clock stretching, the core will now also perform acknowledge-polling after all writes.
This can land after https://github.com/oxidecomputer/transceiver-control/pull/278 and https://github.com/oxidecomputer/quartz/pull/210.