improve buck2 support for yosys flows

[nathanaelhuffman]

Would like to support both a bsv and vhdl flow here. I have little experience with the internals here but with some work I think we can get this going.

We'd want to support both ICE40 and ECP5 devices here, and we'd eventually want to consume a verilog file (output of bsv compile) or a list of VHDL files (output of that transitive set)

Cosmo will still likely have an ice40 on it for some hotplug breakout and it would be nice to generate both fpga images using common toolchains.

[nathanaelhuffman]

192 Covers the very first workflow here, VHDL -> Yosys -> NextPnR -> Icepack. It is still very rough, set up to only generate a bit fite.

We need to better specify desired fmax, output reports etc, but I wanted to get the bones for something in place asap and was able to leverage a lot of the extant buck2 vhdl flow for doing this.