need help with MT7621 cache line size

[GoogleCodeExporter]

Dear friend:
    I see your new commit with MT7621 scache fix，witch number of MIPS_L1_CACHE_SHIFT is right,5 or 6 ? I don't understand why do this change.
    pls help me.

Thanks & Best Regards
lintel

Original issue reported on code.google.com by lintel.h...@gmail.com on 8 Feb 2015 at 11:42

[GoogleCodeExporter]

MT7621 has cache linesize 32 bytes, MIPS_L1_CACHE_SHIFT must be 5. Value 6 is 
bogus hard-coded for MALTA and fixed in upstream. 

https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/commit/?id=a7ef
1eaddbf4bd50bfee92d9dfbecadc61467bbf

Please see MT7621S board bootlog:

kernel: Linux version 3.4.106 (padavan@hms) (gcc version 4.4.7 (GCC) ) #25 SMP 
Thu Feb 12 20:31:32 KRAT 2015
kernel: Ralink SoC: MT7621S, RevID: 0103, RAM: DDR3, XTAL: 40MHz
kernel: CPU/SYS frequency: 880/293 MHz
kernel: CPU revision is: 0001992f (MIPS 1004Kc)
...
kernel: Detected 1 available secondary CPU(s)
kernel: Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
kernel: Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
kernel: MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
...
kernel: Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
kernel: Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
kernel: MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
...

Also cpu_dcache_line_size() and cpu_icache_line_size() return 32.

MT7621 full support is coming soon.

Original comment by andy.pad...@gmail.com on 12 Feb 2015 at 3:24

[GoogleCodeExporter]

Original comment by andy.pad...@gmail.com on 5 Mar 2015 at 8:41

• Changed state: Invalid
• Added labels: Type-Review
• Removed labels: Type-Defect