Vast delays (resulting from infinity values) with stuck-low flipflops and split unateness in liberty timing

This issue was originally affecting us in a proprietary cell library (gf130) but I've managed to make a modified version of Nangate45 that reproduces it. The key is to split the single non_unate timing from CK to Q into two separate entries, one negative_unate when !D&RN with only cell_fall and fall_transition, the other positive_unate when D&RN with only rise timings. This matches the situation in our proprietary library exactly.

The other prerequisite is a stuck-low flipflop (which imperfect optimisations in Yosys sometimes result in, not ideal but something STA should be able to cope with nonetheless) connected to some other logic.

Complete test case with the patched nangate45 library, just run sta.tcl in this archive: flipflop_test_case.zip

Startpoint: b (input port clocked by clk)
Endpoint: q (output port clocked by clk)
Path Group: clk
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
  20.00   20.00 ^ input external delay
   0.00   20.00 ^ b (in)
   0.04   20.04 v nor_i/ZN (NOR3_X1)
38873359834625761509286084188569600.00 38873359834625761509286084188569600.00 ^ inv_i/ZN (INV_X16)
   0.00 38873359834625761509286084188569600.00 ^ q (out)
        38873359834625761509286084188569600.00   data arrival time

 100.00  100.00   clock clk (rise edge)
   0.00  100.00   clock network delay (ideal)
   0.00  100.00   clock reconvergence pessimism
 -20.00   80.00   output external delay
          80.00   data required time
---------------------------------------------------------
          80.00   data required time
        -38873359834625761509286084188569600.00   data arrival time
---------------------------------------------------------
        -38873359834625761509286084188569600.00   slack (VIOLATED)

Some further debugging:

% report_dcalc -from nor_i/A1
Library: NangateOpenCellLibrary
Cell: NOR3_X1
Arc sense: negative_unate
Arc type: combinational
A1 ^ -> ZN v
P = 1.00 V = 1.10 T = 25.00
------- input_net_transition = -INF
|       total_output_net_capacitance = 23.01
|        8.53     16.02
v      --------------------
0.00 | 0.01     0.02
0.00 | 0.02     0.03
Table value = -INF
PVT scale factor = 1.00
Delay = -INF

------- input_net_transition = -INF
|       total_output_net_capacitance = 23.01
|        8.53     16.02
v      --------------------
0.00 | 0.01     0.02
0.00 | 0.01     0.02
Table value = 272121008379618007115665729021542400.00
PVT scale factor = 1.00
Slew = 272121008379618007115665729021542400.00

.............................................

parallaxsw / OpenSTA

Vast delays (resulting from infinity values) with stuck-low flipflops and split unateness in liberty timing #52