ClockTree Arrival time issue

[wuheng01]

case.tar.gz when checking hold violation, we found a strange path which pathend always carray a 0.0 as AT. An example is provided in the attachment. the path is from [get_ports {i_CLK_RTC}] to [get_pins {reg2/D}]

Startpoint: i_CLK_RTC (clock source 'CLK_RTC')
Endpoint: reg2 (rising edge-triggered flip-flop clocked by CLK_PLL)
Path Group: path delay
Path Type: min
Corner: ff

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
     1    1.36    0.00    0.00   -0.48 ^ i_CLK_RTC (in)
                                         i_CLK_RTC (net)
                  0.00    0.00   -0.48 ^ U1/A (CLKBUF_X2)
     1    1.36    0.02    0.05   -0.43 ^ U1/Z (CLKBUF_X2)
                                         n1 (net)
                  0.02    0.00   -0.43 ^ U2/A (CLKBUF_X2)
     1    1.36    0.02    0.06   -0.37 ^ U2/Z (CLKBUF_X2)
                                         n2 (net)
                  0.02    0.00   -0.37 ^ U3/A (CLKBUF_X2)
     2    4.16    0.03    0.07   -0.30 ^ U3/Z (CLKBUF_X2)
                                         n3 (net)
                  0.03    0.00   -0.30 ^ U4/A (BUF_X4)
     1    3.25    0.02    0.05   -0.24 ^ U4/Z (BUF_X4)
                                         n4 (net)
                  0.02    0.00   -0.24 ^ U5/A (BUF_X4)
     1    0.76    0.01    0.04   -0.20 ^ U5/Z (BUF_X4)
                                         n5 (net)
                  0.01    0.00   -0.20 ^ U5_3/A (CLKBUF_X1)
     1    0.76    0.02    0.06   -0.14 ^ U5_3/Z (CLKBUF_X1)
                                         n5_n3 (net)
                  0.02    0.00   -0.14 ^ U5_2/A (CLKBUF_X1)
     1    0.76    0.02    0.07   -0.07 ^ U5_2/Z (CLKBUF_X1)
                                         n5_n2 (net)
                  0.02    0.00   -0.07 ^ U5_1/A (CLKBUF_X1)
     1    1.11    0.02    0.07    0.00 ^ U5_1/Z (CLKBUF_X1)
                                         n5_n1 (net)
                  0.02    0.00    0.00 ^ reg2/D (DFF_X1)
                                  0.00   data arrival time

                          0.00    0.00   min_delay
                          0.02    0.02   library hold time
                                  0.02   data required time
-----------------------------------------------------------------------------
                                  0.02   data required time
                                 -0.00   data arrival time
-----------------------------------------------------------------------------
                                 -0.02   slack (VIOLATED)

which other tools shows:

  Startpoint: i_CLK_RTC (clock source)
  Endpoint: reg2 (rising edge-triggered flip-flop)
  Path Group: in2reg
  Path Type: min

  Point                                    Incr       Path
  ---------------------------------------------------------------
  i_CLK_RTC (in)                        0.00000    0.00000 f
  U1/Z (CLKBUF_X2)                      0.02297    0.02297 f
  U2/Z (CLKBUF_X2)                      0.02445    0.04743 f
  U3/Z (CLKBUF_X2)                      0.02819    0.07562 f
  U4/Z (BUF_X4)                         0.03819    0.11381 f
  U5/Z (BUF_X4)                         0.03281    0.14662 f
  U5_3/Z (CLKBUF_X1)                    0.02134    0.16796 f
  U5_2/Z (CLKBUF_X1)                    0.02203    0.18999 f
  U5_1/Z (CLKBUF_X1)                    0.02295    0.21294 f
  reg2/D (DFF_X1)                       0.00876    0.22170 f
  data arrival time                                0.22170

  min_delay                             0.00000    0.00000
  library hold time                     0.00343    0.00343
  data required time                               0.00343
  ---------------------------------------------------------------
  data required time                               0.00343
  data arrival time                               -0.22170
  ---------------------------------------------------------------
  slack (MET)                                      0.21827

[jjcherry56]

I looks like it because there are ideal clocks (with zero arrival) used as the data input. Please repost the test case with a verilog file so I don't have to use openroad to run it?

[wuheng01]

case.tar.gz I added a verilog file in the attachment.

[jjcherry56]

fixed by 128deaa7 issue66 set_min/max_delay -ignore_clock_latency on clock path

[jjcherry56]

Note that the libraries and corners are not matched (ff with slow lib). It doesn't make much sense to use set_min_delay -ignore_clock_latency for a clock path that in this case is used as a data input.

[icbenchpeng]

This design is from piece of customer case. It is a gated clock path, we just remove the gates that is not needed to reproduce the bug. The clock path detecting methodology still have issues. Other tools will mark the pin not a clock pin if lib say it is not clock, openSTA mark the pin as clock pin. You can see this reg2/D pin is marked as clock pin.

[icbenchpeng]

Clock tree will stop at n5_n1