Closed akashlevy closed 3 months ago
Update: I have a minimal Liberty file that reproduces the problem. It happens when the related_pin
/related_bus_pin
is missing from the timing
group and timing_type
is min_pulse_width
. Have not checked if it happens for other timing_type
s. It seems other STA tools can infer the related_pin
to be self pin (CK
in example below) when not specified, and certain foundries have the related_pin
missing for clock pins. However, this causes OpenSTA to segfault (with a warning).
Here's the minimal example:
/* Autogenerated subset of 5 cells from library below -- DO NOT EDIT MANUALLY */
/*
* ******************************************************************************
* * *
* * Copyright (C) 2004-2011, Nangate Inc. *
* * All rights reserved. *
* * *
* * Nangate and the Nangate logo are trademarks of Nangate Inc. *
* * *
* * All trademarks, logos, software marks, and trade names (collectively the *
* * "Marks") in this program are proprietary to Nangate or other respective *
* * owners that have granted Nangate the right and license to use such Marks. *
* * You are not permitted to use the Marks without the prior written consent *
* * of Nangate or such third party that may own the Marks. *
* * *
* * This file has been provided pursuant to a License Agreement containing *
* * restrictions on its use. This file contains valuable trade secrets and *
* * proprietary information of Nangate Inc., and is protected by U.S. and *
* * international laws and/or treaties. *
* * *
* * The copyright notice(s) in this file does not indicate actual or intended *
* * publication of this file. *
* * *
* * NGLibraryCharacterizer, v2011.01-HR04-2011-01-19 - build 201102050200 *
* * *
* ******************************************************************************
*
* Spice engine : Nanspice v2011.01-HR04-2011-01-19-1102050200
* Liberty export type : conditional
*
* Characterization Corner : fast
* Process : FastFast
* Temperature : 0C
* Voltage : 1.25V
*
****************************************************************************/
library (NangateOpenCellLibrary) {
/* Documentation Attributes */
date : "Thu 10 Feb 2011, 18:11:35";
revision : "revision 1.0";
comment : "Copyright (c) 2004-2011 Nangate Inc. All Rights Reserved.";
/* General Attributes */
technology (cmos);
delay_model : table_lookup;
in_place_swap_mode : match_footprint;
library_features (report_delay_calculation,report_power_calculation);
/* Units Attributes */
time_unit : "1ns";
leakage_power_unit : "1nW";
voltage_unit : "1V";
current_unit : "1mA";
pulling_resistance_unit : "1kohm";
capacitive_load_unit (1,ff);
/* Operation Conditions */
nom_process : 1.00;
nom_temperature : 0.00;
nom_voltage : 1.25;
voltage_map (VDD,1.25);
voltage_map (VSS,0.00);
define(process_corner, operating_conditions, string);
operating_conditions (fast) {
process_corner : "FastFast";
process : 1.00;
voltage : 1.25;
temperature : 0.00;
tree_type : balanced_tree;
}
default_operating_conditions : fast;
/* Threshold Definitions */
slew_lower_threshold_pct_fall : 30.00 ;
slew_lower_threshold_pct_rise : 30.00 ;
slew_upper_threshold_pct_fall : 70.00 ;
slew_upper_threshold_pct_rise : 70.00 ;
slew_derate_from_library : 1.00 ;
input_threshold_pct_fall : 50.00 ;
input_threshold_pct_rise : 50.00 ;
output_threshold_pct_fall : 50.00 ;
output_threshold_pct_rise : 50.00 ;
default_leakage_power_density : 0.00 ;
default_cell_leakage_power : 0.00 ;
/* Default Pin Attributes */
default_inout_pin_cap : 1.000000;
default_input_pin_cap : 1.000000;
default_output_pin_cap : 0.000000;
default_fanout_load : 1.000000;
default_max_transition : 0.146240;
lu_table_template (Pulse_width_3) {
variable_1 : related_pin_transition;
index_1 ("0.0010,0.0020,0.0030");
}
/******************************************************************************************
Module : DFF
Cell Description : Pos.edge D-Flip-Flop with drive strength X1
*******************************************************************************************/
cell (DFF) {
drive_strength : 1;
ff ("IQ" , "IQN") {
next_state : "D";
clocked_on : "CK";
}
area : 4.522000;
pg_pin(VDD) {
voltage_name : VDD;
pg_type : primary_power;
}
pg_pin(VSS) {
voltage_name : VSS;
pg_type : primary_ground;
}
pin (D) {
direction : input;
related_power_pin : "VDD";
related_ground_pin : "VSS";
capacitance : 1.157568;
}
pin (CK) {
direction : input;
related_power_pin : "VDD";
related_ground_pin : "VSS";
clock : true;
capacitance : 0.966728;
timing () {
timing_type : min_pulse_width;
fall_constraint(Pulse_width_3) {
index_1 ("0.000932129,0.0331496,0.146240");
values ("0.025656,0.039623,0.146386");
}
rise_constraint(Pulse_width_3) {
index_1 ("0.000932129,0.0331496,0.146240");
values ("0.029624,0.033183,0.146386");
}
}
}
pin (Q) {
direction : output;
related_power_pin : "VDD";
related_ground_pin : "VSS";
max_capacitance : 60.730000;
function : "IQ";
}
pin (QN) {
direction : output;
related_power_pin : "VDD";
related_ground_pin : "VSS";
max_capacitance : 60.272200;
function : "IQN";
}
}
}
/*
* End of file
*/
Output on my MacBook Pro M2:
akashlevy@Akashs-MacBook-Pro-M2-3 preqorsor-dev % ./opensta/app/sta
OpenSTA 2.6.0 c51fe826d6 Copyright (c) 2024, Parallax Software, Inc.
License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html>
This is free software, and you are free to change and redistribute it
under certain conditions; type `show_copying' for details.
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
% read_liberty test.lib
Warning: test.lib line 140, timing group missing related_pin/related_bus_pin.
zsh: segmentation fault ./opensta/app/sta
I think the fix should be to infer that the related_pin
is the same pin if not specified.
A slightly worse but perhaps easier alternative to implement would be to not make the timing arcs if the timing group is missing related_pin
/related_bus_pin
.
righto 5261a2a9 liberty min_pulse_width missing related_pin
Thanks a lot
No, thank YOU. You did all the work.
Read issue title. I unfortunately cannot attach a full test case as the Liberty file is part of a proprietary PDK and I don't have direct access to it myself. However, I can give a (slightly redacted and demangled) backtrace from
catchsegv
that was sent to me by a customer facing the issue. The file+linenos appear to be incorrect but the function headers might be useful. The binary was compiled with-g
flag on CentOS 7.The customer sent me an example
min_pulse_width
constraint from the problematic Liberty file. Not sure yet if this is the exact one causing the segfault (UPDATE: it is).Sorry that I can't provide a minimal reproducible example yet. Wanted to create this issue to report this bug, in case there are any immediate insights into why this might be happening. I'll be looking into building a small example testcase over the next week (assuming it can't be resolved quickly from inspecting the backtrace).