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parasgidd / avsdpll_3v3

This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—40MHZ to 100MHZ at 1.8v)IP worked on in the VSD Online Internship.
Apache License 2.0
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Ngspice Simulations #1

Open aishwaryapenumarthi opened 3 years ago

aishwaryapenumarthi commented 3 years ago

Hi Paras , It will be helpful if there are different .cir files for 3 frequencies instead of editing in the same one . Steps for ngspice simulations requires little more clarity.

parasgidd commented 3 years ago

Thank you for your valuable feedback, I'll update it to make it more user friendly.