search

parsa-epfl / flexus

Contains the code for the Flexus cycle-accurate simulator, used in QFlex.
https://qflex.epfl.ch
12 stars 9 forks source link

C&S trigger a missing operand1 assertion #53

Open branylagaffe opened 1 month ago

branylagaffe commented 1 month ago

C&S trigger a missing operand1 assertion

Description

C&S instruction may be badly decoded and then trigger an assertion failure.

Steps to Reproduce

  1. Use the latest 1c_MI snapshot

Actual Behavior

casa instruction have only one operand decoded instead of three.

pooriaPoorsarvi commented 4 weeks ago

found the issue in the internal dependency system for one of the operands of CAS (3rd operand). it was setting the internal dep arg to 0 which made one operand mark another one as ready (the first one that was waiting on read register finishing in an extra cycle). Just forcing it to be the correct arg after the fact fixed the issue, investigating more on why arg is being set wrong

pooriaPoorsarvi commented 3 weeks ago

uploaded the fix https://github.com/parsa-epfl/flexus/commit/07010313ea5affbfc44eb515e5adbcdf9869df87

pooriaPoorsarvi commented 3 weeks ago

The bug was caused by one of the actions in C&S (calculating address for RS), and there the operand was set to 1. now even though for the action RS is the only operand, that number is global (with respect to the scope of the instruction), hence the base should have been added (2), since RS is the 3'rd operand (1+2) for the CASA instruction that was being decoded.

branylagaffe commented 3 weeks ago

To be reviewed by @branylagaffe