Add SVE support

[ericvh]

Sorry to not be more specific, you guys have armv8 support, but there's a new Scalable Vector Extension to the archtiecture that's particularly important for HPC and ML. It'd be a nice addition to your tool because its something that's lacking a publicly available analysis framework for. There are some efforts (at Linaro) to integrate it into Qemu, but that's only really good for emulation and it seems like your tool would be more useful for analysis.

[neo-apz]

Thanks for the explanation.

Currently, we are focusing on developing a QEMU based cycle-accurate full-system simulator, which we require for our Computer Architecture research.

Right now, QFlex is trace-based and adding vector arithmetic instructions wouldn't be a significant value-add before the timing model. Once that is ready for release, we can look into adding SVE support in our both trace and cycle-accurate simulators if the QEMU community begins to support it.

[Hnefi]

Hi @ericvh, I just wanted to let you know that we have finally released our QFlex timing model, which allows cycle-level simulation of both the CPU pipeline and a detailed cache hierarchy! You can find it in the master branch of the repo, and a guide on how to use it is available on the website qflex.epfl.ch.

We've seen a lot of SVE instructions being used by libraries in our debugging work (e.g., Google protobuf and even in libc), so this is definitely a feature on our list of additions. We welcome any contributions you might have to the simulator tool, if you are interested in working with us on supporting SVE!