Open Park-Hyung-Joo opened 7 months ago
I am testing the ReRam model written in Verilog-A in ngspice. sky130_reram_cell.txt
when I trace Tfilament_current & t_previous at the start of the loop, they are always 0 for every step of transient loops. Was this issue cleared? I used the 23_05 released version.
I am testing the ReRam model written in Verilog-A in ngspice. sky130_reram_cell.txt
when I trace Tfilament_current & t_previous at the start of the loop, they are always 0 for every step of transient loops. Was this issue cleared? I used the 23_05 released version.