Open mfkasim1 opened 12 months ago
The Compact Model Coalition has a set of Verilog-A files for validating the compiler/simulator. About 40 of the 90 modules have no parameters declared, so OpenVAF crashes. It would be nice to get this fixed.
This is kind of weird. From the stack trace, the error seems to be coming from OsdiNode::to_ll_val
5: 0x5574cb7df3c6 - osdi::metadata::osdi_0_3::OsdiNode::to_ll_val::h8dc42151ca46ac19 at /root/project/openvaf/osdi/src/metadata/osdi_0_3.rs:216
Line 216 is converting the residual_units of the OsdiNode: ctx.const_str_uninternetd(&self.residual_units),
Why is this a problem when there is no parameter in the module?
% git diff openvaf/mir_llvm/src/context.rs diff --git a/openvaf/mir_llvm/src/context.rs b/openvaf/mir_llvm/src/context.rs index cf4f71f..953d825 100644 --- a/openvaf/mir_llvm/src/context.rs +++ b/openvaf/mir_llvm/src/context.rs @@ -80,7 +80,7 @@ impl<'a, 'll> CodegenCx<'a, 'll> { }
pub fn const_str_uninterned(&self, lit: &str) -> &'ll Value {
- let lit = self.literals.get(lit).unwrap();
+ let lit = self.literals.get(lit).unwrap_or_default();
self.const_str(lit)
}
I tried compiling a simple Verilog-A for a capacitor. However, if the file does not have a parameter, it will raise an error. The error can be solved by simply adding a dummy parameter (even though the parameter is useless). Here's an example of the Verilog-A file:
And here's the content of the log file: