The limit function $limit is supposed to take as second argument either a string literal that specifies a simulator specific function,
or the name of an analog function defined in the code. (VAMS standard 9.17.3).
This does currently not work. Attached is an exemplary Verilog-A file.
The limit function $limit is supposed to take as second argument either a string literal that specifies a simulator specific function, or the name of an analog function defined in the code. (VAMS standard 9.17.3).
This does currently not work. Attached is an exemplary Verilog-A file.
hicumL2V2p4p0.txt