Originally posted by **Marvelousmay** January 11, 2023
I used the precompiled standalone executable of Openvaf. Here I tried compiling a comparator model using Verilog-ams language, but I failed, it reported an error like this:
```
# openvaf comparator.va
thread '' panicked at 'internal error: entered unreachable code: attempted to read undefined value', openvaf/mir_llvm/src/builder.rs:112:34
note: run with environment variable to display a backtrace
```
My comparator model is as follows：
```
`include "disciplines.vams"
`include "constants.vams"
module comparator (sigin, sigref, sigout);
input sigin,sigref;
output sigout;
electrical sigin, sigref, sigout;
parameter real sigout_high = 10;
parameter real sigout_low = -10;
parameter real sigin_offset = 0;
parameter real comp_slope = 1000;
analog begin
@( initial_step) begin
if (sigout_high <= sigout_low) begin
$display("Range specification error. sigout_high = (%E) less than sigout_low = (%E).\n",sigout_high,sigout_low);
$finish;
end
end
V(sigout) <+ 0.5 * (sigout_high - sigout_low)* tanh(comp_slope*(V(sigin, sigref) - sigin_offset))+(sigout_high + sigout_low)/2;
end
endmodule
```
I tried another simple model and found that the problem appeared here, and that is that I can only express V like this:
`I(p,n) <+ idt(V(p,n))/L;`
Instead of using:
`V(p,n) <+ L*ddt(I(p,n));`
So when I want to express a V relationship for example:
``V(n2,n1) <+ gain * sin(2 * `M_PI * freq * $abstime);``
How can I modify it?
Looking forward to a reply.
Discussed in https://github.com/pascalkuthe/OpenVAF/discussions/22