analog initial

[KenKundert]

You should support analog initial statements. They are the preferred way of doing initialization of variable in Verilog-A.

[pascalkuthe]

Thank you for bringing this to our attention!

Support for this feature has been added in #43. Our goal is to adhere to the LRM and therefore pointing out missing features like this is very helpful to us. OpenVAF already automatically divides the content of a module's analog statements into an initialization and simulation phase. The analog initial blocks are now automatically prepended to the initialization phase. Our initial focus during development was supporting the CMC compact models and none of these models use analog initial for that purpose, hence we focused on the automatic mechanism and didn't add analog initial yet.