Support analog initial blocks

[pascalkuthe]

OpenVAF already automatically divides the analog block into an initialization phase and simulations phase. The Verilog-AMS language standard includes analog inital statements which can be used to manually move code to the initialization phase when the compiler doesn't perform this portioning automatically. This PR adds support for these to OpenVAF.

Right now all analog initial blocks of a module are simply prepended to the start of the first analog block. The automatic portioning algorithm is optimal and will therefore move all code to the initialization phase. This prevents adding complex new codepaths and ensures we treat edge-cases (like some system function calls) correctly. Once support for hidden state is added we need to be more granular here (likely tagging the MIR will wokr well)

[pascalkuthe]

bors merge

[bors[bot]]

Build failed:

• ci

[pascalkuthe]

bors merge

[bors[bot]]

Build succeeded:

• ci