pascalkuthe
commented
1 year ago Thank you for reporting this issue.
OpenVAF started out with a focus on device models and I slowly expanding the supported subset of the Verilog-A standard. Currently bus nets are not supported by OpenVAF. I would definitly like the support them. There are however two issues:
Firstly simulators (ngspice and xyce) have no notation of a bus so the bus net would need to be represented as multiple individual terminals in ngspice so connection the example model you provided would look as follow:
N1 in0, in1,in2, in3, in4 example_modelThis makes bus nets a lot less useful as multiple Verilog-A models can't be linked together on the simulator level (and OpenVAF doesn't support submodules/connecting modules).
Secondly the Verilog-A standard allows the size of the bus to depend on parameters. That would make the number of nodes in the model non-constant (depend on the parameters). While node collapsing already causes the number of nodes to be variable, this is a specical case. While supporting this in ngspice should not be a problem it would present challenges when integrating with other simulators.
In light of these issues I want to be careful about finding a solution that is compatible with a wide set of simulators while still allowing simulators to add better support for bus terminals in the future. I have a pretty good idea how to implement this into OSDI but landing support for this feature in OpenVAF, OSDI and Ngspice will require a bit of effort.
Until that work is complete you can use the following replacement for input [0:4] in; in your VA code:
input in0, in1,in2, in3, in4;Whenever a net is accessed with in[0] for example you can use in0 instead. This is not quite a perfects substitute but it should cover must usecases which don't involve genvar statements (which are not supported yet as implemented yet)
When attempting bus definitions like this:
I get an error like this:
How should I define a bus to be recognized by openvaf?
Note: Single signals do not generate this error.