pascalkuthe / OpenVAF

An innovative Verilog-A compiler
https://openvaf.semimod.de/
GNU General Public License v3.0
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Setting Parameter Values #84

Closed kdotom closed 1 year ago

kdotom commented 1 year ago

The model compiles, but when I attempt to set the parameters in SPICE, the OSDI model uses the default value as opposed to the value entered in spice.

e.g. for the following module

module testmodule(gnd, o1, i1);
        inout gnd;
        input i1;
        output o1;
        electrical i1, o1, gnd;

        // internal nodes
        electrical n1;

        parameter real x = 0;

        analog begin
                V(n1,gnd) <+ x * V(i1,gnd) * (1e-9);
                V(o1,gnd) <+ V(n1,gnd);
        end
endmodule

with a spice specification of

.model testmodule_model testmodule(x={5})

The simulation result still uses x=0.

Am I missing something or should this work?

metroid120 commented 1 year ago

This is just an ngspice Syntax error. Please see the netlist below with a working example how to use your model:

OSDI Example

V1 in  0 DC 0
R2 out 0 1k

* best syntax:
.model testmodule_model testmodule
+ x=1e9

* works too:
*.model testmodule_model testmodule x=1e9

* does not work:
*.model testmodule_model testmodule(x={5})

N1 0 out in testmodule_model

.control
pre_osdi model.osdi

*op
dc V1 0 2 0.01;
plot v(out)

.endc
.end
kdotom commented 1 year ago

Confirmed. Thanks!